KK11-A Cache Memory

The KK11-A Cache Memory was an option for the KD11-EA CPU, one which added a high-speed cache to the CPU.

Physically, it was a single hex board, the M8268, interfaced to the CPU through an 'over-the-back' connector. (This was because the PDP-11/34 could be field-upgraded from a KD11-E CPU, which did not support the cache, to a KD11-EA, which did - but the original backplane was retained.)

The KK11-A contained 1024 cache entries of high-speed DRAM, in the form of 28 1024x1 DRAM chips. The cache was a direct-mapped cache (i.e. there was only one possible cache entry in which any given word of main memory could be found), with write-through, and a block size of one word.

Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering UNIBUS address bits 17-11); 3 parity bits (one for the tag); and two valid bits (to allow the entire cache to be cleared by switching to a previously cleared set of valid bits).