KDF11-U CPU: Difference between revisions
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The '''KDF11-U''' [[PDP-11 architecture|PDP-11]] CPU for the [[PDP-11/24]] was implemented as a single [[DEC card form factor|hex]] card, the KDF11-UA M7133, using the same 'Fonz' [[F-11 chip set]] as the other [[KDF11 CPUs]]. | The '''KDF11-U''' [[PDP-11 architecture|PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/24]] was implemented as a single [[DEC card form factor|hex]] card, the KDF11-UA M7133, using the same 'Fonz' [[F-11 chip set]] as the other [[KDF11 CPUs]]. | ||
In addition to the basic CPU functionality (including [[PDP-11 Memory Management|memory mapping]] and floating point), it also included sockets to hold a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS), and two serial lines (led out through the backplane). | In addition to the basic CPU functionality (including [[PDP-11 Memory Management|memory mapping]] and [[floating point]]), it also included sockets to hold a 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS), and two [[asynchronous serial lines]] (led out through the [[backplane]]). | ||
There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), to reduce the cost, a number of individual [[ | There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual [[Dual Inline Package|DIPs]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out. | ||
{{PDP-11}} | {{PDP-11}} | ||
[[Category:UNIBUS processors]] | [[Category:UNIBUS processors]] | ||
Revision as of 09:21, 17 December 2017
The KDF11-U PDP-11 CPU for the PDP-11/24 was implemented as a single hex card, the KDF11-UA M7133, using the same 'Fonz' F-11 chip set as the other KDF11 CPUs.
In addition to the basic CPU functionality (including memory mapping and floating point), it also included sockets to hold a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS), and two asynchronous serial lines (led out through the backplane).
There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual DIPs were replaced with a pair of custom gate array chips, and the board was re-laid-out.
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Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |
