Difference between revisions of "KUV11 Writeable Control Store"
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It consists of a [[DEC card form factor|quad]] [[printed circuit board|card]] (M8018) which plugs into the [[QBUS]] [[backplane]] close to the [[Central Processing Unit|CPU]] card, and a [[flat cable]] which runs from the KUV11 to a free micro-[[Read-only memory|ROM]] [[chip socket]] on the CPU card, and gives the KUV11 access to the micro-instruction [[bus]]. | It consists of a [[DEC card form factor|quad]] [[printed circuit board|card]] (M8018) which plugs into the [[QBUS]] [[backplane]] close to the [[Central Processing Unit|CPU]] card, and a [[flat cable]] which runs from the KUV11 to a free micro-[[Read-only memory|ROM]] [[chip socket]] on the CPU card, and gives the KUV11 access to the micro-instruction [[bus]]. | ||
| − | The micro-store consists of 24 1Kx1 high-speed [[static RAM]] [[integrated circuit|chips]] | + | The micro-store consists of 24 1Kx1 high-speed [[static RAM]] [[integrated circuit|chips]]. The LSI-11 micro-[[word]] is 22 bits long; the extra two bits are fed to backplane pins (AE1 and AF1) to provide high-speed controls. A [[Dual Inline Package|DIP]] switch on the KUV11 controls where the micro-store appears in the micro-[[address space]]. |
The micro-words themseves are fed to the LSI-11 over the cable; the LSI-11 does not have the ability to write the micro-store contents over that cable, but has read-write access to it via the QBUS. That bus also provides access to a number of control [[register]]s on the KUV11. | The micro-words themseves are fed to the LSI-11 over the cable; the LSI-11 does not have the ability to write the micro-store contents over that cable, but has read-write access to it via the QBUS. That bus also provides access to a number of control [[register]]s on the KUV11. | ||
| − | The principle hardware debugging aid is the 'micro-[[address]] trace [[Random Access Memory|RAM]]', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the micro-word. | + | The principle hardware debugging aid is the 'micro-[[address]] trace [[Random Access Memory|RAM]]', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the extended micro-word. |
==Further reading== | ==Further reading== | ||
Revision as of 17:27, 26 November 2018
The KUV11 Writeable Control Store is an option for the LSI-11 which provides a user-programmable microcode memory extension, along with some hardware aids to debugging micro-programs. It allows additional, custom instructions to be added to the PDP-11 instruction set.
It consists of a quad card (M8018) which plugs into the QBUS backplane close to the CPU card, and a flat cable which runs from the KUV11 to a free micro-ROM chip socket on the CPU card, and gives the KUV11 access to the micro-instruction bus.
The micro-store consists of 24 1Kx1 high-speed static RAM chips. The LSI-11 micro-word is 22 bits long; the extra two bits are fed to backplane pins (AE1 and AF1) to provide high-speed controls. A DIP switch on the KUV11 controls where the micro-store appears in the micro-address space.
The micro-words themseves are fed to the LSI-11 over the cable; the LSI-11 does not have the ability to write the micro-store contents over that cable, but has read-write access to it via the QBUS. That bus also provides access to a number of control registers on the KUV11.
The principle hardware debugging aid is the 'micro-address trace RAM', which is a 16-entry record of consecutive micro-addresses emitted as the micro-program runs, which can be frozen under program control, using one of the two extra bits in the extended micro-word.
Further reading
- LSI-11 WCS User's Guide, EK-KUV11-TM-001
| v • d • e PDP-11 Computers and Peripherals |
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| UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
| UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |
