KD11-E CPU: Difference between revisions

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Clarify/expand KY11-LB interface
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==KY11-LB Interface==
==KY11-LB Interface==


The interface to the KY11-LB is carried over two 10-wire [[flat cable]]s connected to [[Berg connector]] headers (denominated J1 and J2) on the M7266 module.
The microcode diagnostic interface to the KY11-LB is carried over two 10-wire [[flat cable]]s connected to [[Berg connector]] headers (denominated J1 and J2) on the M7266 module. (The main functionality of the KY11-B is done over the UNIBUS, and several backplane lines.)


==See also==
==See also==

Revision as of 20:01, 9 January 2019

The KD11-E CPU was the first CPU version for the PDP-11/34; it consisted of two hex printed circuit boards, the M7265 Data Paths module and the M7266 Control module.

Although it supported the KY11-LB Programmer's Console, including the maintainence functionality which allow the CPU's microcode to be single-stepped, it did not support the FP11-A floating point unit or the KK11-A cache; a PDP-11/34 system needed the upgraded KD11-EA CPU for that.

KY11-LB Interface

The microcode diagnostic interface to the KY11-LB is carried over two 10-wire flat cables connected to Berg connector headers (denominated J1 and J2) on the M7266 module. (The main functionality of the KY11-B is done over the UNIBUS, and several backplane lines.)

See also