KDF11-U CPU: Difference between revisions

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The '''KDF11-U''' is the [[PDP-11 architecture|PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/24]]; it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It was implemented as a single [[DEC card form factor|hex]] card, the KDF11-UA M7133, using the same 'Fonz' [[F-11 chip set]] as the other [[KDF11 CPUs]].
The '''KDF11-U''' is the [[PDP-11 architecture|PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/24]]; it used the [[UNIBUS]], unlike the [[QBUS]] of the other [[KDF11 CPUs]]. It was implemented as a single [[DEC card form factor|hex]] card, the KDF11-UA '''M7133''', using the same 'Fonz' [[F-11 chip set]] as the other KDF11 CPUs.


In addition to the basic CPU functionality (including [[PDP-11 Memory Management|memory mapping]] and [[floating point]]), it also included sockets to hold a 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS), and two [[asynchronous serial line]]s (led out through the [[backplane]]).
In addition to the basic CPU functionality (including [[PDP-11 Memory Management|memory mapping]] and [[floating point]]), it also included sockets to hold a 6-chip carrier implementing the [[PDP-11 Commercial Instruction Set]] (CIS), and two [[asynchronous serial line]]s (led out through the [[backplane]]).


There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual [[Dual Inline Package|DIPs]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.
There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual [[Dual Inline Package|DIP]] [[integrated circuit|chips]] were replaced with a pair of custom [[gate array]] chips, and the board was re-laid-out.


{{PDP-11}}
{{PDP-11}}

Revision as of 15:49, 23 January 2020

The KDF11-U is the PDP-11 CPU for the PDP-11/24; it used the UNIBUS, unlike the QBUS of the other KDF11 CPUs. It was implemented as a single hex card, the KDF11-UA M7133, using the same 'Fonz' F-11 chip set as the other KDF11 CPUs.

In addition to the basic CPU functionality (including memory mapping and floating point), it also included sockets to hold a 6-chip carrier implementing the PDP-11 Commercial Instruction Set (CIS), and two asynchronous serial lines (led out through the backplane).

There are two different versions of the KDF11-U; in the later M7133-YA (documented in the manual EK-11024-TM-003, Appendix D), in order to reduce the cost, a number of individual DIP chips were replaced with a pair of custom gate array chips, and the board was re-laid-out.