MSV11-Q QBUS memory

MSV11-QA card, later etch

The MSV11-Q (M7551) is a quad-height QBUS DRAM main memory card. Initially it used 64Kx1 DRAM chips, later ones uses 256Kx1 DRAMs. The memory is arranged as 8 banks, each 16 data bits (1 PDP-11 word) wide, with 2 additional bits for parity (1 per byte).

It holds 1 MByte with 64K DRAMs; 4 Mbytes when fully populated with 256K DRAMs, or 2 Mbytes when half-populated (the only partially-filled configuration allowed). Three versions exist:

• MSV11-QA, 1 Mbyte (64K DRAMs)
• MSV11-QB, 2 Mbytes (256K DRAMs)
• MSV11-QC, 4 Mbytes (256K DRAMs)

all are Q22, and support block mode. The -QA comes in two etch revisions; the latter version supports battery backup. The -QB and -QC are the same etch as the later -QA.

Control Register

Each board has a single control register, which can be configured in the range 172100-172136.

In the register contents (below), all the bits can be read and written by software; most are cleared by power up and bus INIT. Bits which can only be modified by the CPU are shown in normal font, and those which can also be set by the hardware in italics.

Parity Error	Extended Error Address Enable	Reserved		Error Address							Reserved		Write Wrong Parity	Reserved	Parity Error Enable
15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00

The 'Error Address' field contents depend on the setting of the 'Extended Error Address Enable' bit; when it holds the low address ('Extended Error Address Enable' is 0), it holds address bits 11 through 17; when it holds the high address ('Extended Error Address Enable' is 1), it holds bits 21 through 18 - bits 11-9 of the register are unused.

Technical information

As far as is known, there are no copies of the engineering drawings extant for the MSV11-Q. However, some technical information, enough to repair boards with faulty DRAM chips, has been gathered on it, and that is made available here.

As described above, each board has 8 (sometimes 4) banks in the array of DRAM chips; with 64K chips, each bank is thus 128KB; with 256K chips, they are 512KB. (Note that the MSV11-Q sends a 'write' to all the banks, and selects the one to actually use by use of the RAS signal. It's not certain why DEC did this, but since there is no 'read' signal, and likely the outputs from all the banks are wire-OR'd together, use of RAS to select the bank works for read as well as write.)

The chips in each bank run across the board (when it is oriented with the chip side facing the viewer, with the metal edging holding the handles at the bottom). Bit 0 (value 1) is on the right hand edge of the array; bit 15 (value 0100000) is on the left, with the two parity bits in the middle. The banks run up the board from the metal handle edge; bank 0 is next to the handles, and bank 7 is up near the contact fingers.

The following 64K DRAM chips have been observed to be used: M5K4164ANP-15P (Micron Technologies), NEC D4164C211 (NEC Electronics).

Further reading

• MSV11-QA, MSV11-QB, and MSV11-QC Field Maintenance Printset (MP-01931)