PDP-11/45

A PDP11-45

The PDP-11/45 was a fast UNIBUS PDP-11 system based on the KB11-A CPU. The PDP-11/50 and PDP-11/55 used the same processor, but featuring a MS11 MOS or bipolar MOS memory, respectively.

Optionally, the machine could be configured with an FP11 floating-point processor, and a KT11-C memory management unit.

The machine had an 18-bit UNIBUS, allowing it to address 256KiW of memory.

KB11-A CPU

The KB11-A was a high-performance CPU implemented in MSI TTL logic.

Documentation

• EK-KB11A-MM-xxx KB11-A Central Processor Unit Maintenance Manual

hampage.hu

Quoting: Introduced two years after the PDP-11/20, in June 1972. The KB11 was a faster, microcoded CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.

The cycle time of the /45 with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.

The /50 was basically the same machine with different memory. The /55 (KB11D) used the modified CPU of the /70, where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the /70, but only had a 18-bit addressing range. It was the fastest of the "classic" -11 CPU's when measured by the cycle times.

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