KT11-B Paging Option

The KT11-B Paging Option is an option for the PDP-11/20, produced by DEC's Computer Special Systems group.

It allows the -11/20 to run time-sharing at the basic machine level; hardware features in the CPU prevent any user from interfering with the overall operation of the system. It does this by providing two modes for the CPU, 'User' and 'Exec', with certain operations (e.g. halting the machine) being dis-allowed in User mode.

It also allows the system to use up to 248 Kbytes of memory (the maximum allowed by the UNIBUS), although only a maximum of 64 KBytes is accessable (i.e. in the CPU's address space) at any one time. By proper programming, the mapping may be set so that user processes cannot interfere with each other's memory.

As an additional feature, pages may be marked 'Private', which means that only access from code running in Private pages are allowed; i.e. information in such pages is hidden from code in 'Public' pages. Control may be transferred from code running in Public pages only at 'entry points', locations which contain a particular instruction ("BR .+2").

Architecture

In both Exec and User mode, when the KT11-B is enabled, the address space is divided up into 128 virtual pages of 512 bytes each. Similarly, the potential 248 Kbytes of physical memory are divided into 496 physical pages, each of which can hold a page of virtual memory contents. (In other words, pages of virtual memory cannot be assigned to arbitrary locations in physical memory, but must always be in blocks which start on 512 byte boundaries.)

Page maps, stored in main memory, map from virtual pages to physical pages; each map contains 128 entries, one for each virtual page. Each page map entry contains a 9 bit physical page number in the low bits, and a 3 bit 'protection key' in the high bits.

The key controls which types of access are allowed to that virtual page; bit 13 is Write Enable, bit 14 is Public, and bit 15 is Resident (the virtual page is currently contained in a physical memory page, i.e. the low bits of the entry are valid).

Implementation

The KT11-B is interposed between the KA11 CPU, and the rest of the system (memory and devices). There are two UNIBUSes, joined by the KT11-B; the UNIBUS from the CPU runs into the KT11-B, which processes UNIBUS cycles before passing them through to another UNIBUS, which holds all the memory, devices, etc.

The KA11 CPU of the -11/20 is also slightly modified, and a cable carries signals between the KA11 and KT11-B.

A page entry cache in the KT11-B (invisble to software) holds the 8 most-recently-used page table entries. (An option increases the size of the cache to 24 entries, which can reduce the amount of memory bandwidth 'wasted' on cache refills.) The cache is divided into an associative memory, 8 bits wide (7 bits of page number, and 1 Exec/User bit), and a scratchpad, 16 bits wide. Scrachpad entries hold page table entries; each associative memory entry contains the page number for the matching scratchpad entry.

Programming

The KT11-B is controlled by a bank of eleven registers:

Address	Name	Function
777572	KTWN	Window
777574	KTMR	Maintenance
777576	KTCS	Status and Control
777600	KTIC	Instruction Counter
777602	KTSP	Stack Pointer
777604	KTPC	Program Counter
777606	KTPS	Program Status
777610	KTAD	Address
777612	KTDT	Data
777614	KTUM	USER Map Control
777616	KTEM	EXEC Map Control

Note that these occupy the same locations as the standard PDP-11 Memory Management registers; 77757x are SSR0-2, and 7776xx are user PDRs.

Construction

The KT11-B is composed of a large number of single width FLIP CHIPs, most of them simple, generic ones; they are plugged into a custom wire-wrapped backplane.