PDP-11/84

The PDP-11/84 is the UNIBUS-capable twin to the QBUS-only PDP-11/83; both used the KDJ11-B CPU (with its PMI bus). The -11/84 added a KTJ11-B UNIBUS adapter to provide its UNIBUS, and had a main backplane which was half QBUS, and half UNIBUS, with a slot in the middle for the KTJ11-B.

The backplane contains (in order) four quad-heightslots, the first of which is a custom slot, and the others are PMI (technically Q22/CD, although slightly modified from the normal form of that in this backplane, see below); they are used for (in order, from the front of the machine):

• the Machine Debug Monitor board (M7677); this slot is not numbered
• the CPU board; this is slot 1
• main memory board
• optional second main memory board

and nine hex-height slots, used for:

• UNIBUS adaptor, in slot 4
• four SPC slots
• three MUD slots
• UNIBUS 'out' and quad SPC slot, in slot 12

Note that the PMI slots do not have the bottom-up ordering of PMI-capable slots in a Q22/CD backplane, but are wired as a true bus, allowing the 'CPU, memory, memory' insertion ordering.

Note also that in the normal configuration (see below for details), the QBUS bus grant lines are not routed through the memory slots, so if a slot is unused, there is no need for a jumper card in that slot.

On most UNIBUS backplanes, the 'NPG' (DMA grant line) signal is carried across unused slots by wire jumpers on the wire-wrap pins on the back side of the backplane; on the -11/84 backplane, they are brought out to a DIP switch on the MDM module.

QBUS slots

The two main memory slots can in fact be configured as regular Q22/CD QBUS slots, by removing two jumpers. EK-PDP84-TM-PR4 (PDP-11/84 Technical Manual) says (in section 2.1.14, "Backplane (H9277-A)", pg. 2-6):

Bus signals BDMGI (pin AR2) and BIAKI (pin AM2) for slots 2 & 3 are jumpered on the front of the backplane.

There are indeed two jumpers, W1 and W2 (in the upper right-hand corner, when facing the backplane from the board insertion side); the traces connected to them are on the surface, so it is possible to see where they go: one end runs to a trace connected from slot 1 to slot 2, and the other to a trace connected from slot 3 to slot 4; those connect to AM2 (BIAKI) and AN2 (BIAKO), and AR2 (BDMGI) and AS2 (BDMGO).

Thus, when the jumpers are in, the CPU's BIAKO/BDMGO pins are connected directly to the UNIBUS adapter's BIAKI/BDMGI pins; when they are out, those signals are routed through the two 'memory' slots, in the normal QBUS manner. It therefore seems those two slots can function as real QBUS slots. (If not, why arrange things so that the can run grant lines through them?) As far as is known, this has not yet been verified, though.

As to why DEC put this capability in, and then didn't more widely document it, or use it: that is not known. Perhaps they thought it would introduce extra complixity in the user instructions, or something.

hampage.hu

PDP-11/84

Quoting: Introduced in 1988. Based on the J-11 chip set, DEC originally wanted the clock speed to be 20MHz, but it couldn't be done on time, so the actual speed was 18MHz. It was the fastest CPU of the PDP-11's anyhow. The high-end configuration had up to 4MB RAM on PMI (Private Memory Interconnect) and a floating-point accelerator.

The UNIBUS-based PDP-11/84 was for those customers, who wanted more I/O throughput or had some legacy equipment.

The box on the picture to the left is a BA123 which was a popular enclosure for qbus machines. Apart from the 12x4-slot qbus backplane, it had five slots for storage units, e.g. room for two or three harddisks, a tape drive (TK50 here) and floppy.

Gallery