PDP-11/23

A PDP-11/23

The PDP-11/23 was the second QBUS PDP-11 system; it used the KDF11-A CPU (M8189).

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Quote: Introduced in 1979. Intended as the successor of the PDP-11/03. Based on the F-11 chip set, it had a dual-height KDF11-A CPU card. The memory management was 22 bit (4MB address space), but in some revisions (KDF11-A Rev. A) only 18 lines were used. The LSI-11/23 instruction set consists of 97 standard and 46 optional floating point instructions. The microcycle time of the CPU is around 300 ns.

The PDP-11/23-PLUS used the quad-height KDF11-B CPU module, which had two asynchronous serial lines and boot PROMs on-board.

The KDF11-A module has four 40-pin sockets for the chipset. One is for the DCF11 two-chip hybrid (21-15541AB data path and 23-001C7 control chip), one's for the KTF11 MMU option and one's for the KEF11 floating-point option (another two-chip carrier; the MMU chip must be installed to use the FPP option). The remaining socket can be used with the CIS option, which spans two sockets wide (so you loose the FPP). The KDF11-B has five sockets, so there are no problems with this.

In floating-point-heavy applications, the FPF11 can be used. This is a quad-height module that is connected to the KEF11-socket on CPU board with a cable. It's based on bitslice processors, the performance is six times of the performance of the KEF11 option. (64-bit data path, 17-digit accuracy)

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