KA11 CPU
The KA11 is the CPU of the PDP-11/20, the first PDP-11.
It was the only PDP-11 CPU which was not micro-programed (since the cheap ROMs which make micro-programming cost-effective in smaller machines were not available at the time it was designed).
Internal structure
The KA11 is basically divided into four main sections:
- Bus Interface
- Data Paths
- Registers
- Control
The first and last communicate with the machine's main bus, the UNIBUS.
There is a 16x16 register file, of which half are used to hold the machine's general registers; two of the others are used for internal temporary registers (Temp and Source). A number of other internal registers (e.g. the Bus Address Register) are implemented separately, so they are always available.
State machine
As noted above, the KA11 does not have microcode; instead, it uses a state machine to control the operation of the CPU. There are 5 major states:
- Fetch - obtain and decode the instruction;
- Source - decode the source field of a double-operand instruction, fetch the data, and store it in a temporary;
- Destination - decode the destination field, and obtain the data;
- Execute - use the data obtained in previous states to perform the requested operation, including writing data back to the desination;
- Service - perform special operations such as interrupts, traps, etc.
Not all instructions pass through all 5 states, although all do pass through 'Fetch'.
Implementation
The KA11 was implemented as a set of extended length FLIP CHIPs; most of the circuuitry was on quad-height ones, but there were some duals, and a few singles.
They all plugged into a custom backplane, formed from three 4-slot backplane sections wired together into one monolithic unit.
The KA11 board set comprises:
Board | Function |
---|---|
Single | |
M823 | Codes Data |
M825 | Power Failure and Control |
Dual | |
M224 (two instances) | Data Paths (8 bits; 2 latches, adder) |
M225 | Registers (16 bits x 16) |
M821 | Register Control |
M822 | Flag Control |
M824 | Priority |
Quad | |
M724 | Bus and Console Control |
M725 | Bus Interface and IR |
M726 | IR Decode |
M727 | State Control |
M728 | Timing and States |
M820 | Data Path Control |
v • d • e PDP-11 Computers and Peripherals |
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UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 PDP-11/05 • PDP-11/10 • PDP-11/04 • PDP-11/34 • PDP-11/60 • PDP-11/44 • PDP-11/24 • PDP-11/84 • PDP-11/94 QBUS PDP-11s - PDP-11/03 • PDP-11/23 • PDP-11/23+ • MicroPDP-11/73 • MicroPDP-11/53 • MicroPDP-11/83 • MicroPDP-11/93 QBUS CPUs: LSI-11 • LSI-11/2 • KDF11-A • KDF11-B • KDJ11-A • KDJ11-B • KDJ11-D • KDJ11-E Buses: UNIBUS • UNIBUS map • SPC • MUD • EUB • QBUS • CD interconnect • PMI Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FP11 floating point • PDP-11 Memory Management |
UNIBUS CPUs: KA11 • KC11 • KB11-A • KB11-B • KB11-C • KB11-D • KD11-A • KD11-B • KD11-D • KD11-E • KD11-EA • KD11-K • KD11-Z • KDF11-U
Co-processors: FP11-A • FP11-B • FP11-C • FP11-E • FP11-F • KE44-A • FPF11 Chips: LSI-11 • KEV11-A • KEV11-B • KEV11-C • F-11 • KEF11-A • KTF11-A • T-11 • J-11 • FPJ11 CPU options: KE11-E • KE11-F • KJ11-A • KT11-C • KT11-D • KK11-A • KK11-B • KT24 • KTJ11-B Rare CPU options: KS11 Memory Protection and Relocation option • KT11-B Paging Option • KUV11 Writeable Control Store Front panels: KY11-A • KY11-D • KY11-J • KY11-LA • KY11-LB • KY11-P More on buses: UNIBUS and QBUS termination • Bus Arbitration on the Unibus and QBUS • CTI BUS PDT-11s - PDT-11/110 • PDT-11/130 • PDT-11/150 CTI PDP-11s - PRO-325 • PRO-350 • PRO-380 Other: FIS floating point • PDP-11 Commercial Instruction Set • PDP-11 stacks • PDP-11 family differences |