KB11-B CPU

The KB11-B CPU is the earlier CPU for the PDP-11/70. The optional FP11-B Floating-Point Processor (full FP11 floating point), and up to four RH70 MASSBUS controller plugged into the CPU's backplane.

The KB11-B used a special memory bus, unique to the -11/70, for its bus to main memory; this bus allowed it to have up to 4 mega-bytes of main memory. All devices were attached to a separate UNIBUS; DMA devices could gain access to the memory via a UNIBUS map which connected the two, and also mapped UNIBUS addresses to main memory addresses. High-speed devices could be attached to MASSBUS controllers.

Full PDP-11 Memory Management and a cache were standard on all KB11-B's.

Boards

The basic KB11-B consisted of fifteen hex boards:

• M8130 Data Paths
• M8131 General Registers and ALU Control
• M8132 Instruction Register Decode and Condition Codes
• M8133 ROM and ROM Control
• M8134 Processor Data and UNIBUS Registers
• M8135 Trap and Miscellaneous Control
• M8136 UNIBUS and Console Control
• M8137 System Address Paths
• M8138 System Status Registers
• M8140 System Descriptor/Console Control
• M8141 UNIBUS Map
• M8142 Cache Control
• M8143 Address Memory
• M8144 Data Memory
• M8145 Cache Data Paths

and a quad board:

• M8139 Timing Generator

The M8130 through M8139 boards are based on those of the KB11-A CPU of the PDP-11/45, upon which the KB11-B is based; the rest implement the -11/70's extensions (cache - M8142-45, UNIBUS Map - M8141, etc).

See also

• KB11-C CPU