LSI-11

The LSI-11 was DEC's first cost-reduced PDP-11 CPU, using the QBUS and the LSI-11 chip set. The LSI-11 is a quad board (M7264) with additional functionality on-board. They were popular in OEM usage.

The usual CPU options were available for the LSI-11: the KEV11-A, for the EIS/FIS instructions; the KEV11-B provides EIS without FIS; the KEV11-C provides a subset of the PDP-11 CIS (it also apparently includes the EIS, but not the FIS).

It also supported the optional KUV11 Writeable Control Store.

The chip order (from the left, with the contact finger edge down, and the component side facing the viewer) is KEV11, uROM 1, uROM 0, Control, Data Path.

Many different LSI-11 models exist, including the KD11-F and KD11-H base versions, and numerous other variants. The KD11-F version includes 4KW of MOS RAM; the KD11-H version has the RAM deleted.

Others included various KEV11 chips: the KD11-L includes the KEV11-A, and the KD11-Q includes the KEV11-C. Some models include additional cards: e.g. the KD11-J referred to an LSI-11 sold with an MMV11-A QBUS core memory card, and the KD11-R to one with an MSV11-C QBUS MOS memory card.

ODT

They were the first PDP-11 model to not have a front panel to control them; instead, as a cost-reduction measure, when the CPU is halted, specialized microcode used the main serial line as a operating console. The command set is named Octal Debugging Technique (ODT); there are commands to read and write main memory, start the CPU, etc.

The main serial interface is normally configured so that when the CPU is running, sending a break on the console serial line halts the CPU.

Links

• LSI-11 Processors