Difference between revisions of "KD11-E CPU"

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The interface to the KY11-LB is carried over two 10-wire [[flat cable]]s connected to [[Berg connector]] headers (denominated J1 and J2) on the M7266 module.
 
The interface to the KY11-LB is carried over two 10-wire [[flat cable]]s connected to [[Berg connector]] headers (denominated J1 and J2) on the M7266 module.
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==See also==
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* [[KD11-E/EA microcode]]
  
 
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Revision as of 19:02, 8 January 2019

The KD11-E CPU was the first CPU version for the PDP-11/34; it consisted of two hex printed circuit boards, the M7265 Data Paths module and the M7266 Control module.

Although it supported the KY11-LB Programmer's Console, including the maintainence functionality which allow the CPU's microcode to be single-stepped, it did not support the FP11-A floating point unit or the KK11-A cache; a PDP-11/34 system needed the upgraded KD11-EA CPU for that.

KY11-LB Interface

The interface to the KY11-LB is carried over two 10-wire flat cables connected to Berg connector headers (denominated J1 and J2) on the M7266 module.

See also