Difference between revisions of "PDP-11/24"

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The '''PDP-11/24''' was the last low-end [[UNIBUS]] [[PDP-11]] system. The KDF11-UA CPU of the -11/24 was also implemented as a single [[DEC card form factor|hex]] card, the M7133; it used the same 'Fonz' chip-set as the [[QBUS]] [[PDP-11/23]].
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The '''PDP-11/24''' was the last low-end [[UNIBUS]] [[PDP-11]] system. It used the same 'Fonz' chip-set as the [[QBUS]] [[PDP-11/23]]; the KDF11-UA CPU of the -11/24 was implemented as a single [[DEC card form factor|hex]] card, the M7133.  
  
Like the earlier [[PDP-11/44]], the -11/24 supported up to 4 Mbytes of main memory, using an [[Extended UNIBUS]] between the CPU and memory; all devices were attached to a semi-separate (see below) [[UNIBUS]]. An optional UNIBUS MMap provided access to all of memory for UNIBUS DMA devices.
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Like the earlier [[PDP-11/44]], the -11/24 supported up to 4 Mbytes of main memory, using the [[Extended UNIBUS]] between the CPU and memory; all devices were attached to a semi-separate (see below) [[UNIBUS]]. An optional UNIBUS Map provided access to all of memory from UNIBUS DMA devices.
  
 
==UNIBUS Map==
 
==UNIBUS Map==
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A set of 31 mapping register pairs in the KT24 mapped 8 Kbyte blocks of UNIBUS address space to any location within the 4 Mbyte main memory address space.
 
A set of 31 mapping register pairs in the KT24 mapped 8 Kbyte blocks of UNIBUS address space to any location within the 4 Mbyte main memory address space.
  
If no KT24 was present, the CPU detected its absence, and statically mapped the UNIBUS address space across to the low 256 Kbytes of EUB main memory, using a cross-connection path on the CPU card.
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If no KT24 was present, the CPU detected its absence, and statically mapped the UNIBUS address space across to the low 248 Kbytes of EUB main memory, using a cross-connection path on the CPU card.
  
 
==System bus structure==
 
==System bus structure==
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Either the CPU, or the optional KT24, provided a path from the UNIBUS to the EUB for DMA access to main memory by devices.
 
Either the CPU, or the optional KT24, provided a path from the UNIBUS to the EUB for DMA access to main memory by devices.
  
The top 256 Kbtes of the CPU's address space were devoted to the UNIBUS; the top 8 Kbytes of that were, as usual, the I/O space.
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The top 256 Kbtes of the CPU's address space were devoted to the UNIBUS; the top 8 Kbytes of that were, as usual, the peripheral page.
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===Implementation===
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The -11/24 used a custom 9-slot backplane; slot 1 was for the CPU, slot 2 could hold either memory or the UNIBUS map; slots 3-6 could hold either memory or [[Small Peripheral Controller|SPC]]devices. Slots 7-8 were ordinary MUD/SPC slots, and slot 9 was an ordinary SPC/UNIBUS Out slot.
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The EUB and UNIBUS address lines were kept separate in all the slots which supported the EUB (1-6); the data lines seem to have been cross-connected between the SPC and EUB portions. (That is because EUB memory boards pick up the data lines on [[DEC card form factor#Edge connector contact identification|connector A]], whereas SPC devices get them on connector C - and the memory/SPC slots can hold either. The CPU boards connects to the data bus on the C connector.)
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==Packaging==
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The -11/24 came in two different cabinets, the 5-1/4 inch high [[BA11-L]] and the 10-1/2 inch [[BA11-A]] (the same box as used in the -11/44).
  
 
{{PDP-11}}
 
{{PDP-11}}
  
 
[[Category:UNIBUS processors]]
 
[[Category:UNIBUS processors]]

Revision as of 15:47, 23 July 2016

The PDP-11/24 was the last low-end UNIBUS PDP-11 system. It used the same 'Fonz' chip-set as the QBUS PDP-11/23; the KDF11-UA CPU of the -11/24 was implemented as a single hex card, the M7133.

Like the earlier PDP-11/44, the -11/24 supported up to 4 Mbytes of main memory, using the Extended UNIBUS between the CPU and memory; all devices were attached to a semi-separate (see below) UNIBUS. An optional UNIBUS Map provided access to all of memory from UNIBUS DMA devices.

UNIBUS Map

The optional UNIBUS Map, the KT24, provided a path between the UNIBUS and the EUB; the KT24 was also implemented as a single hex card, the M7134.

A set of 31 mapping register pairs in the KT24 mapped 8 Kbyte blocks of UNIBUS address space to any location within the 4 Mbyte main memory address space.

If no KT24 was present, the CPU detected its absence, and statically mapped the UNIBUS address space across to the low 248 Kbytes of EUB main memory, using a cross-connection path on the CPU card.

System bus structure

As mentioned, the -11/24 used an EUB for the bus between the memory and the CPU, and the UNIBUS for the bus between the CPU and devices. The two busses were not entirely separated; they shared a set of data lines, with each bus having a separate set of address lines.

Either the CPU, or the optional KT24, provided a path from the UNIBUS to the EUB for DMA access to main memory by devices.

The top 256 Kbtes of the CPU's address space were devoted to the UNIBUS; the top 8 Kbytes of that were, as usual, the peripheral page.

Implementation

The -11/24 used a custom 9-slot backplane; slot 1 was for the CPU, slot 2 could hold either memory or the UNIBUS map; slots 3-6 could hold either memory or SPCdevices. Slots 7-8 were ordinary MUD/SPC slots, and slot 9 was an ordinary SPC/UNIBUS Out slot.

The EUB and UNIBUS address lines were kept separate in all the slots which supported the EUB (1-6); the data lines seem to have been cross-connected between the SPC and EUB portions. (That is because EUB memory boards pick up the data lines on connector A, whereas SPC devices get them on connector C - and the memory/SPC slots can hold either. The CPU boards connects to the data bus on the C connector.)

Packaging

The -11/24 came in two different cabinets, the 5-1/4 inch high BA11-L and the 10-1/2 inch BA11-A (the same box as used in the -11/44).