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A PDP-11/70
Manufacturer: Digital Equipment Corporation
Year Introduced: March 1975
Word Size: 16 bit
Physical Address Size: 22 bit
Virtual Address Size: 16 bit
Bus Architecture: UNIBUS/MASSBUS/memory bus

The PDP-11/70 was a very high performance UNIBUS PDP-11 system; it basically took the high-performance CPU of the PDP-11/45 (implemented in SSI Schottky TTL logic), and augmented it with:

  • A 2 Kbyte, 300 nsec cache, organized as 2-way set associative, with 4-byte blocks, connected to what had been the FastBus high-speed memory interface on the PDP-11/45 CPU
  • The ability to support up to 4 Mbytes of main memory via a new Main Memory Bus, and changes to the CPU to allow access to that much memory
  • A UNIBUS map to allow devices on the UNIBUS access to all of that memory
  • The ability to support up to 4 RH70 MASSBUS controllers, which connected high-speed secondary storage devices directly to the main memory, bypassing the UNIBUS

The CPU was the KB11-B (in early units, prior to 1976) or KB11-C (later) CPU. (The difference between the two was whether they took the optional FP11-B or FP11-C FPP.)

Main memory

The main memory systems supported by the -11/70 were the MJ11 memory system (which used core memory), and the later MK11 memory system (which used dynamic RAM).

The Main Memory Bus consisted of transmission lines, which required terminators on both ends; at the MJ11/MK11 end, a pair of H873 modules were plugged into the last output port, to do that.

The cabling used for the Main Memory Bus (DEC part number 70-10824) consists of a set of four BC06R-xx flat cables; two for the address and control, and two for the data. They run from Berg connector headers on boards in the KB11 CPU's cache to others on boards in the MJ11/MK11.


Quote: Introduced in March 1975, the PDP-11/70 is the bigest of the PDP-11s. The KB11B is a re-enginered version of the PDP-11/45's CPU, with some new features. Two of the most important changes was the addition of cache (2 KByte of bipolar memory) and the 22-bit memory management. The latter enables the usage of memory up to 2 Mwords, using the UNIBUS map, which translates 18-bit UNIBUS addresses to 22-bit physical addresses. The kernel/supervisor/user operating modes and the MMU was standard. Important options: FPP, MASSBUS adapters (RH70's, up to four) with direct memory access.

The original processor had the floating point unit of the PDP-11/45, which turned out to be ineffective, so it was resdesigned (KB11C). Overall performance is 0.6th of the VAX-11/780.

A normal system occupied at least two H960 cabinets (memory and CPU), the UNIBUS expansion needed another. There were also later revisions sold in another cabinet, without the front panel (Datasystem 570?).

Trivia: The original business plan called for 1000 PDP-11/70's to be built, it was supposed to be a "stopgap" until the "wide word machine" came out. This "word wide machine" was originally a small PDP-10 (36-bit machine), but it was then cancelled in favor of the 32-bit VAX. Anyhow, more than 10,000 PDP-11/70's were built.


A mock up PDP-11/70 front panel PDP-11/70 sales ad Pdp11 70a.jpg Pdp11 70b.jpg Pdp11-70c.jpg

Further reading

  • PDP-11/70 maintenance and installation manual, EK-11070-MM-002

External links