The basic clock μcycle is 350 nsec; simple register-register instructions (e.g. MOV, ADD) took 3.5 μseconds; depending on the exact operand modes used in a particular instruction, and the main memory speed (with the asynchronous QBUS), that could add up to roughly 12 μseconds to that basic time. (The extra time is roughly linear in the number of memory cycles, at 1.4-2.1 μseconds per cycle - depending on the operand modes, PDP-11 instructions could add up to 6 additional memory cycles per instruction, above the 1 needed to fetch the basic instruction.)
Note that ODT will not function correctly in the LSI-11s unless there is main memory on the QBUS (at location 0). The reason for this restriction is unknown: the KDF11 CPUs and KDJ11 CPUs, which also use ODT, do not have this limitation; e.g. a system consisting only of a KDF11-A CPU and a serial console will run ODT.
Both LSI-11s are Q16 devices; they only drive 16 address lines. Although they can be plugged into a Q18 or Q22 backplane, they will only function with Q16 or Q18 main memory. (With Q22 memory, the pins used for BDAL18-21 are used for other, internal signals by the LSI-11.)
There were CPU options were available for the LSI-11s: the KEV11-A, for the EIS/FIS instructions; the KEV11-B provides EIS without FIS; the KEV11-C provides a subset of the PDP-11 CIS (it also apparently includes the EIS, but not the FIS).
They also supported the optional KUV11 Writeable Control Store.
- Mark J. Sebern, A Minicomputer-Compatible Microcomputer System: The DEC LSI-11, in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, Computer Engineering: A DEC View of Hardware Systems Design, Digital Press, Bedford, 1978
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Also: PDP-11 architecture • PDP-11 Extended Instruction Set • FIS floating point • FP11 floating point • PDP-11 Commercial Instruction Set • PDP-11 Memory Management • PDP-11 stacks • PDP-11 family differences