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• MS11-M MOS memory
  ...h automagically corrects single-[[bit]] errors, (at a 70 nsec penalty in [[access time|response time]] when an error occurs) and detects double-bit errors. T The [[access time]] is normally 490-525 nsec (typical/max; 620-675 nsec extra on [[memor
  3 KB (473 words) - 20:02, 30 July 2023
• Extended UNIBUS memories
  ...automagically correct single-[[bit]] errors, and (at a slight penalty in [[access time|response time]] when an error occurs) detect double-bit errors.
  694 bytes (101 words) - 15:54, 6 February 2024
• Ram
  #Redirect [[Random Access Memory]]
  34 bytes (4 words) - 16:41, 21 October 2018
• Real mode
  ...er architecture, long mode is the mode where a 64-bit operating system can access 64-bit instructions and registers. ... Real mode or virtual 8086 mode progr
  3 KB (536 words) - 16:57, 19 January 2023
• Port
  * [[hardware port]] - a means of gaining access to a computer or a sub-system
  275 bytes (40 words) - 13:11, 19 December 2023
• Hardware port
  A '''port''', in [[hardware]] is a means of gaining access to a computer or a sub-system.
  473 bytes (79 words) - 04:30, 13 December 2018
• RP10 disk controller
  ...ys paired with a [[DF10 Data Channel]] unit which performs [[Direct Memory Access|DMA]] to [[main memory]].
  1 KB (184 words) - 21:59, 8 March 2023
• RP01 disk drive
  | average access time = 62.5 msec
  1 KB (156 words) - 00:32, 15 August 2023
• Channel
  ...Unit|CPU]]; they are connected to [[peripheral]]s, and usually have direct access to [[main memory]]. ...inframe]] systems; on smaller machines, mechanisms such as [[Direct Memory Access|DMA]] from [[device controller]]s do a lot of what a channel does.
  1 KB (205 words) - 17:18, 9 April 2024
• Relay
  ...n pairs of [[contact]]s (which are connected to other pins, for electrical access). How many pairs, and whether they are open or closed when incoming voltage
  1 KB (167 words) - 05:08, 14 December 2018
• RH10 MASSBUS controller
  ...ys paired with a [[DF10 Data Channel]] unit which performs [[Direct Memory Access|DMA]] to [[main memory]].
  1,023 bytes (148 words) - 13:05, 12 November 2023
• FPF11 floating point processor
  That socket gives the FPF11 access to both the [[data bus]] and the [[microinstruction]] bus on the CPU card.
  2 KB (383 words) - 02:31, 12 October 2022
• Project MAC
  ...ious expansions, originally 'Mathematics and Computation'; later 'Multiple Access Computer', 'Machine Aided Cognition', and 'Man and Computer' were added) wa
  788 bytes (105 words) - 10:22, 10 January 2024
• RS64 disk drive
  | average access time = 16.9msec (60Hz), 20.3msec (50Hz)
  2 KB (258 words) - 22:12, 14 August 2023
• RS03/04 disk drive
  | average access time = 8.5 msec (60Hz), 10.2 msec (50Hz)
  3 KB (488 words) - 18:37, 14 August 2023
• LSI-11 chip set
  ...chip also contains [[condition codes]] logic, and a data port which gives access to the [[QBUS]]' data/[[address]] lines.
  5 KB (773 words) - 22:42, 20 December 2023
• IMP11-A ARPANET interface
  ...ox]] holding a pair of [[DR11-B parallel interface]]s (the [[Direct Memory Access|DMA]] type of DR11 - one for [[packet]] input, and one for output), and a c
  3 KB (338 words) - 04:19, 30 August 2022
• KY11-A Programmer's Console
  ...the [[UNIBUS]], either for an [[interrupt]], or performing [[Direct Memory Access|DMA]].
  2 KB (386 words) - 01:41, 6 July 2023
• CSMA-CD
  #Redirect [[Carrier-Sense Multiple Access with Collision Detection]]
  68 bytes (7 words) - 01:49, 6 December 2018
• CSMA
  #Redirect [[Carrier-Sense Multiple Access with Collision Detection]]
  68 bytes (7 words) - 01:50, 6 December 2018
• DASD
  #REDIRECT [[Direct Access Storage Device]]
  42 bytes (5 words) - 17:27, 18 December 2018
• Interlan NI1010A/NI2010A Ethernet Communications Controller
  They use [[Direct Memory Access|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They hav
  6 KB (797 words) - 21:11, 17 August 2022
• KD11-K CPU
  ...PDP-11 memory management]], and used a [[UNIBUS]] for its [[main memory]] access (although a built-in [[cache]] was standard). ...indicates (pg. 4) that devices that do [[interrupt]]s and [[Direct Memory Access|DMA]] must be connected to the I/O UNIBUS, and not to the memory UNIBUS; bu
  4 KB (536 words) - 12:34, 11 October 2022
• PDP-10 memories
  ...[channel]]s for [[mass storage]], such as [[disk]]s, to do [[Direct Memory Access|DMA]]. [[Memory interleaving|Interleaving]] was generally supported between
  3 KB (431 words) - 03:27, 31 July 2023
• MD10 core memory
  ...0 could contain two to four 32KW memory modules, for a maximum of 128KW; [[access time]] is 0.8 μseconds, and the [[cycle time]] is a maximum of 1.8 μsecon
  1 KB (231 words) - 13:54, 2 August 2023
• MA10 core memory
  ...16KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.55 μseconds, and a [[cycle time]] of .93 µseconds. It connect
  1 KB (165 words) - 13:53, 2 August 2023
• MB10 core memory
  ...16KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.60 μseconds, and a [[cycle time]] of 1.65 µseconds. It connec
  881 bytes (134 words) - 13:53, 2 August 2023
• ME10 core memory
  ...ovided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.0
  1 KB (181 words) - 13:55, 2 August 2023
• MF10 core memory
  ...64KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.61 μseconds, and a [[cycle time]] of 0.95 µseconds.
  2 KB (271 words) - 12:37, 5 November 2023
• MG10 core memory
  ...imum of 128KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .67 μseconds maximum, and the [[cycle time]] is 1.0 μseconds; [
  2 KB (342 words) - 12:33, 5 November 2023
• MH10 core memory
  ...imum of 256KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .74 µseconds, and the [[cycle time]] is 1.18 µseconds; [[parity
  3 KB (407 words) - 12:40, 5 November 2023
• VGA
  *256 [[kilobyte|KB]] Video [[Random-access memory|RAM]] (The very first cards could be ordered with 64 KB or 128&
  11 KB (1,681 words) - 12:41, 27 February 2024
• Microsoft BASIC
  ...l 5150. The entry-level version of the 5150 came with just 16 KB of random-access memory (RAM), which was sufficient to run Cassette BASIC. However, Cassette ...sident code of Cassette BASIC.[2] It added functions such as diskette file access, storing programs on disk, monophonic sound using the PC's built-in speaker
  9 KB (1,473 words) - 03:37, 16 January 2024
• MF20 MOS memory
  The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[c
  2 KB (278 words) - 15:50, 24 October 2022
• MG20 MOS memory
  <!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[c
  2 KB (355 words) - 15:49, 24 October 2022
• HP BASIC
  ...ies&nbsp;— 2000A, 2000B, 2000C, High-Speed 2000C, 2000E, 2000F, and 2000/Access.
  2 KB (342 words) - 19:30, 20 June 2023
• RH20 MASSBUS controller
  ...ccess to the main memory of the system, to allow it to use [[Direct Memory Access|DMA]] to move data directly from devices to main memory, without needing CP
  2 KB (294 words) - 12:59, 12 November 2023
• Arbitration
  ...the process of deciding which of several competing entities will be given access to a particular resource. In [[hardware]], there are two basic ways to do t
  395 bytes (59 words) - 08:30, 19 March 2023
• Able UNIVERTER
  ...two busses are roughly identical (e.g. in [[interrupt]]s, [[Direct Memory Access|DMA]], etc); only the low-level details differ. (E.g. the UNIBUS carries [[
  2 KB (251 words) - 18:32, 5 December 2022
• DP11-A Synchronous Line Interface
  The two SYNC registers overlay the buffer registers; access to them is gained via byte UNIBUS operations to odd addresses.
  6 KB (849 words) - 04:17, 18 February 2023
• PRIMOS
  Lore found in the printer bin: "In heaven they have instant access computers, in hell they have Primes."
  2 KB (256 words) - 13:59, 28 September 2019
• Bus Arbitration on the Unibus and QBUS
  ...in the system, either so they can access memory directly ([[Direct Memory Access|DMA]]) or so they can [[interrupt]] the processor and give it an [[interrup DEC's DC010 Direct Memory Access Logic chip [10] uses a delay line just like this but since delay lines are
  21 KB (3,685 words) - 04:35, 28 November 2023
• DM11 Asynchronous 16-line Single-Speed Multiplexer
  ...asynchronous serial line interface|DH11]], in that it used [[Direct Memory Access|DMA]]. ...ven in ones not directly accessible from the UNIBUS); DMA was used to gain access to it. (Perhaps this was early enough in time that [[gate]]s for [[flip-flo
  8 KB (1,088 words) - 02:24, 19 February 2023
• KA650 Main Memory System
  ...lly refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh. ...the KA650. There is no assertion of CAS since there is no need to actually access a specific location, just to refresh a given row.
  42 KB (5,491 words) - 12:55, 7 May 2024
• MXV11-A Multifunction Option Module
  * MXV11-AA - 8Kbytes of [[Random Access Memory|RAM]]
  2 KB (301 words) - 20:47, 13 July 2023
• MXV11-B Multifunction Option Module
  The board contains 128Kbytes of [[Random Access Memory|RAM]]; it can hold a pair of 2, 4, 8 or 16KB ROMs.
  2 KB (322 words) - 13:13, 17 February 2023
• DRV11-B Direct Memory Access Interface
  ...[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.
  3 KB (380 words) - 03:54, 10 June 2020
• MSV11
  * [[MSV11-L MOS Random-Access Memory|MSV11-L]] * [[MSV11-P MOS Random-Access Memory|MSV11-P]]
  616 bytes (99 words) - 21:28, 2 July 2023
• MSV11-L MOS Random-Access Memory
  [[Access time]] is 210-230 nsec for reads, and 90-120 nsec for writes; [[cycle time]
  6 KB (926 words) - 14:10, 22 September 2022
• MSV11-L
  #Redirect [[MSV11-L MOS Random-Access Memory]]
  46 bytes (6 words) - 04:15, 7 May 2020
• MSV11-P
  #Redirect [[MSV11-P MOS Random-Access Memory]]
  46 bytes (6 words) - 13:42, 7 May 2020
• Three cycle data break
  '''Three cycle data break''' was a form of [[Direct Memory Access|DMA]] for high-speed [[peripheral]]s (usually [[mass storage]]) to [[main m
  1 KB (235 words) - 22:06, 15 June 2022
• RS08 disk drive
  | minimum access time = 260 usec (60Hz)<br>320 usec (60Hz) | average access time = 15.9 msec (60Hz)<br>20.3 usec (60Hz)
  1 KB (173 words) - 22:13, 14 August 2023
• DRV11-WA General Purpose DMA Interface
  ...[[bit]] parallel ports, one input, and one output. It uses [[Direct Memory Access|DMA]] to transfer data; it is a [[QBUS#Variable address size|Q22]] device. To gain access to the BAE, reference the BAR; this sets an internal flag which sends the n
  4 KB (529 words) - 19:12, 2 December 2021
• DHV11 asynchronous serial line interface
  ...epending on the cabling option chosen (below). Output used [[Direct Memory Access|DMA]] (with each line having its own [[buffer]] [[pointer]] and count); inp
  6 KB (894 words) - 11:33, 17 February 2023
• MINI-UNIX
  ...up on the LSI-11. (The main significant difference is that in the LSI-11, access to the [[Processor Status Word|PS]] requires use of special [[instruction]] * 'raw devices' (which can do [[Direct Memory Access|DMA]] transfers directly from the device to a buffer in the user process' m
  8 KB (1,243 words) - 21:16, 21 June 2023
• LSX
  * 'raw devices' (which can do [[Direct Memory Access|DMA]] transfers directly from the device to a buffer in the user's process)
  7 KB (1,142 words) - 08:14, 8 November 2022
• DHQ11 asynchronous serial line interface
  ...erface|RS-232]] [[asynchronous serial line]]s. Output used [[Direct Memory Access|DMA]] (with each line having its own [[buffer]] [[pointer]] and count); inp
  2 KB (383 words) - 11:47, 17 February 2023
• DHU11 asynchronous serial line interface
  ...interface|RS-232]] [[asynchronous serial line]]s, and used [[Direct Memory Access|DMA]] on the output side.
  5 KB (710 words) - 02:28, 19 February 2023
• Type 340 Precision Incremental Display
  ...d to an [[array]] of command [[word]]s) could be read with [[Direct Memory Access|DMA]]; standard in the PDP-4 and -7, optional in the -1. (Connection to the
  2 KB (242 words) - 03:27, 4 March 2024
• PWB/UNIX
  * addition of the access(), tell(), alarm(), pause() and setpgrp() [[system call]]s (these seem to h
  7 KB (1,109 words) - 16:49, 27 September 2023
• Digital ETHERNET Q-Bus Network Adapter
  * DEC DC336 QBUS Interface/[[Direct Memory Access|DMA]] Controller ([[DEC part number]] 21-21427-01)
  1 KB (157 words) - 23:31, 17 August 2022
• MA20 core memory
  ...mum of 128KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.00 µseconds, and the [[cycle time]] is 1.92 µseconds (both fo
  1 KB (191 words) - 04:17, 1 August 2023
• MM11-B core memory
  ...ing|interleave]] a pair of MM11-B's to provide reduced effective average [[access time]]s.
  3 KB (462 words) - 00:45, 30 July 2023
• MM11-C core memory
  ...ing|interleave]] a pair of MM11-C's to provide reduced effective average [[access time]]s.
  2 KB (414 words) - 00:46, 30 July 2023
• RF08 disk controller
  ...S08 drives. It used the [[three cycle data break]] form of [[Direct Memory Access|DMA]] to transfer data directly to [[main memory]]. Data transfers can rang
  525 bytes (79 words) - 20:26, 6 May 2021
• DF32 disk controller
  ...S32 drives. It used the [[three cycle data break]] form of [[Direct Memory Access|DMA]] to transfer data directly to [[main memory]].
  831 bytes (138 words) - 00:50, 30 April 2021
• PDP-4
  | memory speed = 2 μsec ([[access time]])<br>8 μsec (read/write [[cycle time]]) [[Direct Memory Access]] for high-speed devices was provided by the [[three cycle data break]] mec
  6 KB (775 words) - 20:00, 7 February 2024
• Tandberg TDV 2215
  To access the setup menus, hold down the CTRL key and press the HELP key twice in qui
  3 KB (388 words) - 18:55, 16 May 2021
• PDP-8 Memory Extension units
  ...ng bits, to select the field, during the [[Central Processing Unit|CPU]]'s access to memory: the Instruction Field and associated Instruction Buffer Register ...Register, a 3 bit wide register used during [[data break]] [[Direct Memory Access|DMA]] operations, to select the field those cycles go to.
  4 KB (614 words) - 21:02, 7 August 2022
• DA10 Twelve- and Eighteen-Bit Computer Interface
  .... Unlike the [[DL10 PDP-11 Data Link|DL10]], it didn't use [[Direct Memory Access|DMA]], just [[programmed I/O]]. The device's priority level for [[interrupt
  3 KB (442 words) - 14:51, 7 March 2023
• DQ11 NPR Synchronous Line Interface
  The ''' DQ11''' is the earliest [[Direct Memory Access|DMA]] [[synchronous serial line]] [[peripheral|interface]] for the [[UNIBUS The DQ11 has a set of 16 'shadow' registers, access to which is gained by placing the shadow register number in the appropriate
  8 KB (1,222 words) - 04:17, 18 February 2023
• DTE20 Ten-Eleven Interface
  ...to the PDP-11 (both to reduce the load on the main CPU, but also to allow access to the wide range of peripherals supported on the PDP-11); or it can also f ...nnected to the EBox of the KL10 via the EBus; privileged DTE20's also have access to the diagnostic section of the KL10's Ebus. To the PDP-11, it appears as
  2 KB (410 words) - 13:14, 12 November 2023
• DMV11 Synchronous Controller
  ...line]] [[peripheral|interface]] for the [[QBUS]]. It used [[Direct Memory Access|DMA]] to transfer data. It could operate in either [[half-duplex]] or [[ful
  4 KB (508 words) - 03:39, 16 February 2023
• DV11 Communications Multiplexer
  ...cond. It used a 'microprocessor' to drive the lines, using [[Direct Memory Access|DMA]] to the [[PDP-11]]'s [[main memory]] for both input and output. |Secondary Register Access Register || DVSRAR || 775010
  6 KB (823 words) - 04:24, 18 February 2023
• MM11-Y core memory
  ...ing|interleave]] a pair of MM11-Y's to provide reduced effective average [[access time]]s.
  2 KB (244 words) - 00:47, 30 July 2023
• CB-UNIX
  Multiple access user space was a subset of a more general shared memory mechanism (below); * smcreat(path, access, size)
  3 KB (489 words) - 01:31, 30 December 2022
• Grant continuity card
  ...use [[bus grant line]]s as part of their [[interrupt]]- or [[Direct Memory Access|DMA]]-handling mechanisms. They go in otherwise-empty slots in the [[backpl
  554 bytes (82 words) - 22:39, 3 December 2021
• BCC 500
  ...icrocode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory. The microcode implements an [[instruction set]] with a
  2 KB (319 words) - 17:44, 29 April 2024
• ANTS terminal system
  ...hard-wired and via dial-up [[modem]]s, allowing [[user]]s at the terminals access to the [[time-sharing]] hosts attached to the ARPANET), ANTS machines provi .../800280.811033 The ARPA Network Terminal System: A New Approach to Network Access], in ''DATACOMM '73: Proceedings of the third ACM symposium on Data communi
  2 KB (283 words) - 03:12, 30 June 2022
• ELF operating system
  ...It allowed [[process]]es to be created and terminated, and allowed them access to inter-process communication and timers; allocation and freeing of [[main ...anford.edu/file/druid:jg594pg0466/jg594pg0466.pdf online] at Stanford, but access to it seems to currently be restricted
  3 KB (461 words) - 16:23, 14 October 2022
• Terminal Interface Processor
  ...could be attached [[terminal]]s, which allowed [[user]]s at the terminals access to the hosts attached to the ARPANET.
  2 KB (262 words) - 20:25, 17 December 2023
• LH-DH/11 Local/Distant Host Controller
  The '''LH-DH/11 Local/Distant Host Controller''' is a [[Direct Memory Access|DMA]] [[UNIBUS]] [[1822 interface]] produced by [[Advanced Computer Communi
  3 KB (427 words) - 17:17, 8 November 2021
• MLH-DH/LSI11 Multiple Channel Controller
  The '''MLH-DH/LSI11 Multiple Channel Controller''' is a [[Direct Memory Access|DMA]] [[QBUS]] [[IMP interface]] produced by [[Advanced Computer Communicat
  3 KB (443 words) - 16:35, 8 November 2021
• Packet Radio Network
  ...to-IMP Protocol]] used by the IMPs, PRUs used an alternative, the 'Channel Access Protocol' (CAP), which also includes some of the control mechanisms of the
  4 KB (557 words) - 20:49, 29 January 2024
• ANTS/ISI IMP Interface
  ...ovided an [[1822 interface]] for the [[UNIBUS]] which used [[Direct Memory Access|DMA]] to transfer data to/from [[main memory]].
  4 KB (500 words) - 23:27, 12 November 2021
• LSI-11 Bus interface chips
  * DC010 - [[Direct Memory Access]] Logic (19-14038-00)
  2 KB (254 words) - 00:40, 13 July 2023
• DMA Request and Grant
  ...ontrol of the QBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle.
  1 KB (190 words) - 04:01, 21 November 2021
• M9047 grant continuity card
  It carried not only the [[Direct Memory Access|DMA]] grant line [[DMA Request and Grant‎‎|DMG]], but also the [[interr
  551 bytes (94 words) - 12:59, 3 December 2021
• Gateway
  [[Application]] [[layer]] devices which allowed users on one side access to similar, but different, services on the other side were also commonly ca
  638 bytes (95 words) - 18:30, 30 November 2021
• DR11-W
  #Redirect [[DR11-W Direct Memory Access Interface]]
  51 bytes (7 words) - 17:44, 2 December 2021
• DR11-W Direct Memory Access Interface
  ...[[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device. It was a single [[DEC card form fa .../www.bitsavers.org/pdf/dec/unibus/EK-DR11W-UG-004.pdf DR11-W Direct Memory Access Interface Module User's Guide] (EK-DR11W-UG-004)
  5 KB (746 words) - 17:48, 2 December 2021
• DR11-W Direct Memory Interface
  #REDIRECT [[DR11-W Direct Memory Access Interface]]
  51 bytes (7 words) - 17:41, 2 December 2021
• Datapoint 2200
  ...I' machine. When planning for the 2200 started, [[semiconductor]] [[Random Access Memory|RAM]] did not exist yet. Datapoint was using large [[shift register]
  5 KB (814 words) - 20:05, 4 June 2023
• BLISS
  ...all'' references to a variable evaluate to the variable's [[address]]; for access to the ''contents'', it was necessary to explicitly use the 'contents of' [ ...the original became '''BLISS-10'''. Because of BLISS's goals of providing access to low-level aspects of the host machine, it required changes for the PDP-1
  3 KB (416 words) - 19:05, 8 December 2021
• DX11-B System 360/370 Channel to PDP-11 Unibus Interface
  ...ystem/370|370]] or compatible machine. On the PDP-11 side, [[Direct Memory Access|DMA]] is used to transfer data.
  2 KB (305 words) - 16:23, 22 January 2024
• KLESI Low-End Storage Interconnect
  <!-- They have an identical programming interface; both use [[Direct Memory Access|DMA]] to transfer information between [[main memory]] and the device.
  2 KB (244 words) - 20:58, 23 April 2024
• BA11-P card cage
  ...net produced by DEC; the BA11-P's (up to two per M9500) swung out for full access, not on slides as with the other BA11's.
  1 KB (228 words) - 03:23, 11 July 2023
• DA11-F UNIBUS Window
  ...ectly connected, to allow bus read/write cycles (including [[Direct Memory Access|DMA]] cycles) from a master on one to be answered by a slave on the other;
  3 KB (513 words) - 00:01, 14 January 2022
• DA11-B DMA UNIBUS Link
  In Block Mode, the DA11-B uses [[Direct Memory Access|DMA]] on the source bus to read words in the block, and then uses DMA on th
  2 KB (286 words) - 04:26, 30 August 2022
• DEC Semiconductor Chips
  | [[Direct Memory Access]] [[#ref_12|[12]]][[#ref_14|[14]]] | MicroVAX Direct Memory Access (DMA) [[#ref_12|[12]]][[#ref_14|[14]]]
  36 KB (3,420 words) - 05:36, 5 November 2022
• M7850 parity controller
  Memory [[access time]] on read is increased by 150 nsec if there is no error, and by 200 ns
  3 KB (434 words) - 00:07, 20 April 2024
• TENEX sharable save file
  | Access Access bits:
  2 KB (342 words) - 17:07, 6 April 2022
• M7259 Parity Control Module
  It provides byte parity. Memory [[access time]] on read is increased by 125 nsec if parity is enabled.<!-- if there
  4 KB (621 words) - 22:21, 6 July 2022
• ITS PDUMP format
  | Access Access bits:
  1 KB (214 words) - 23:15, 5 April 2022
• UA11 Unibus Analyzer
  ...ear; also, all UNIBUS signals are brought up un header pins for convenient access.
  1 KB (174 words) - 15:31, 9 April 2022
• DUMPER tape format
  | Access
  5 KB (703 words) - 12:29, 27 April 2022
• Record
  ...cord-structured' [[input/output|I/O]] (as opposed to the arbitrary storage access now provided by [[UNIX]] and descendant systems, which allow the user to bu
  536 bytes (80 words) - 01:27, 19 April 2022
• Living Computer Museum
  ...of the COVID pandemic, it has unfortunately suspended operations. Remote access remains open to the public.
  2 KB (217 words) - 17:55, 14 January 2024
• THE VAXORCIST
  TSR: Colorado Customer Support. What is your access number, please?
  15 KB (2,569 words) - 08:21, 20 May 2022
• Customizing VMS V1.0
  Logicals are usually used to access system files in their standard places.
  22 KB (3,202 words) - 23:17, 5 September 2022
• TC01 DECtape Control
  ...ended for use with the [[TU55 DECtape Transport]]. It is a [[Direct Memory Access|DMA]] interface, using [[three cycle data break]]; it generates [[interrupt
  900 bytes (137 words) - 14:35, 30 May 2022
• TC08 DECtape Controller
  ...TC08N''', is for PDP8's with a 'negative I/O bus'. It is a [[Direct Memory Access|DMA]] interface, using [[three cycle data break]]; it generates [[interrupt
  1 KB (162 words) - 14:36, 30 May 2022
• Playing DUNGEON on VMS V1.0
  NOT BE TRANSPARENT. FOR YOU TO ACCESS (E.G., TAKE) AN OBJECT SIZES. YOU MAY PUT ANY OBJECT YOU HAVE ACCESS TO (IT NEED NOT BE
  8 KB (1,230 words) - 12:20, 24 July 2022
• VAX-11/750 & VAX-11/751 Revision Control
  in queue access.
  101 KB (10,182 words) - 14:04, 2 July 2022
• VAXcluster
  ...and the dual porting of disk devices. Thus, a single point of failure for access to a disk device could be avoided when VAXcluster configurations were first
  13 KB (1,908 words) - 19:25, 27 April 2024
• RA73 disk drive
  | average access time = 27 msec
  2 KB (233 words) - 10:28, 31 August 2023
• Installing, Configuring, and Testing DECnet V1.3 on VMS V2.0
  ===Remote File Access===
  15 KB (1,849 words) - 16:06, 20 September 2022
• NCP DECnet/VAX V1.3
  ACCESS PRIVILEGES: ACCESS PRIVILEGES:
  28 KB (3,686 words) - 19:40, 16 November 2023
• Computer Interconnect
  ...o uses [[Carrier-Sense Multiple Access with Collision Detection|CSMA]] for access control to the shared transmission medium, but different in detail from tha
  3 KB (442 words) - 20:42, 14 May 2024
• DMC11 Synchronous Serial Controller
  The DMC11 uses [[Direct Memory Access|DMA]] to transfer data. It can operate in either [[half-duplex]] or [[full-
  2 KB (324 words) - 22:46, 13 May 2023
• Ethernet transceiver
  * the Ethernet Transceiver '''MAU''' (for: '''Media Access Unit'''), and
  3 KB (426 words) - 22:08, 17 August 2022
• DEC Ethernet Transceivers
  ...is very inconvenient to mount the unit to a Thickwire segment difficult to access, e.g. located in a ceiling plenum.
  6 KB (955 words) - 17:02, 11 June 2022
• RA72 disk drive
  | average access time = 27 msec
  2 KB (233 words) - 10:29, 31 August 2023
• RA71 disk drive
  | average access time = 27 msec
  2 KB (233 words) - 10:30, 31 August 2023
• VCB01 Video Controller
  ...led video memory), is 256 kB of [[Metal Oxide Semiconductor|MOS]] [[Random Access Memory|RAM]], residing in the Q22-bus address space.
  2 KB (217 words) - 21:50, 13 February 2024
• System call
  ...ode of the [[Central Processing Unit|CPU]], to which the users do not have access, so that they may be protected from each other), the process must use some
  863 bytes (135 words) - 14:27, 27 June 2022
• VAX-11/785 Revision Control
  in queue access.
  118 KB (7,116 words) - 14:05, 2 July 2022
• VAX-11/780 & VAX-11/782 Revision Control
  o M8272 C provides random longword aligned 32 bit access capability in queue access.
  70 KB (7,782 words) - 14:04, 2 July 2022
• Advanced Installation of Ultrix V2.0 on SIMH
  Gateway Access = Enabled
  73 KB (9,059 words) - 20:56, 22 May 2023
• ULTRIX Remote Installation Service
  The RIS server must have access to a suitable load device for tape media, e.g. a [[TK50]] or a 9-track [[ma
  1 KB (217 words) - 10:28, 8 July 2022
• ULTRIX Diskless Mangement Services
  ...ervers provide software that client systems, which may not have disks, can access across the network. Another feature of DMS is that one client can have access to more than one diskless environment.
  1 KB (225 words) - 09:33, 8 July 2022
• ULTRIX Remote Console
  ** The service password needed to gain access to the target node
  2 KB (341 words) - 20:02, 3 July 2022
• Installing and Configuring an ULTRIX V3.0 DMS Server on a SIMH MicroVAX 3900
  be given access permission to this directory, or a null list to systems you wish to access. First list the name of the remote host
  80 KB (9,795 words) - 09:39, 10 July 2022
• MAC Address
  #Redirect [[Media Access Control Address]]
  42 bytes (5 words) - 09:51, 9 July 2022
• Media Access Control Address
  '''Media Access Control Addresses''' (usually shortened to the acronymic form, '''MAC Addre
  1 KB (162 words) - 01:15, 11 July 2022
• Media Access Control address
  #Redirect [[Media Access Control Address]]
  42 bytes (5 words) - 01:15, 11 July 2022
• MAC address
  #Redirect [[Media Access Control Address]]
  42 bytes (5 words) - 01:16, 11 July 2022
• RZ22 disk drive
  | average access time = 33.4 msec
  763 bytes (95 words) - 21:47, 18 February 2024
• Digital Storage Architecture
  ...e purposes. The software to hardware interface is referred to as the port "access protocol." | +-----------+ | Access | +-----------+ |
  6 KB (698 words) - 21:26, 18 August 2023
• Extended Memory Interconnect
  ...[multi-processor]]. The bus has special capabilities to support the shared access to memory required by such a system.
  3 KB (491 words) - 01:43, 8 May 2024
• Installing, Configuring, and Testing A VMS V4.7 Local Area VAXcluster on SIMH
  space, you may decompress them for faster access. Use SYS$UPDATE:LIBDECOMP.COM
  112 KB (13,727 words) - 18:09, 30 January 2024
• Static RAM
  ...hardware]] level). The lack of refresh also means that it has a constant [[access time]] - there is never a need to wait for a refresh cycle to complete. ...[[bit-mapped display]]s, etc - anyplace where speed and a guaranteed fixed access time are critical. In the early days of [[personal computer]]s, it was some
  1 KB (183 words) - 02:06, 20 September 2022
• DMR11 Synchronous Controller
  ...ine]] [[peripheral|interface]] for the [[UNIBUS]]. It uses [[Direct Memory Access|DMA]] to transfer data to and from [[main memory]]. The DMR11 can operate i
  2 KB (315 words) - 23:54, 13 May 2023
• Standard Disk Interconnect
  * Automatic Revectoring for transparent access to replaced blocks.
  4 KB (512 words) - 15:29, 29 December 2023
• HSC50 Hierarchical Storage Controller
  With certain restrictions, the HSC50 allows two or more processors to access files on the same disk.
  9 KB (1,370 words) - 23:47, 28 December 2023
• VSV11 Graphic System
  ...[display program]] held in [[main memory]]. The VSV11 used [[Direct Memory Access|DMA]] to retrieve the display program from the system's main memory, and co
  3 KB (390 words) - 12:39, 27 February 2024
• DW11 UNIBUS-to-LSI-11 Bus Converter
  ...of a [[UNIBUS]] to a [[QBUS]]. Normal master/slave cycles, [[Direct Memory Access|DMA]] cycles, and [[interrupt]]s can all pass through the DW11. It was a [[
  1 KB (232 words) - 02:50, 31 August 2022
• PDP-10 Memory Bus
  For [[Direct Memory Access|DMA]], [[mass storage]] peripherals connected directly to memories (PDP-10
  3 KB (409 words) - 13:38, 12 November 2023
• List of SITS system calls
  | Access,,sphere (C)
  3 KB (444 words) - 23:45, 26 March 2023
• VDH/11 Very Distant Host Controller
  ...been gathered by examining extant [[device driver]]s) is a [[Direct Memory Access|DMA]] [[UNIBUS]] [[synchronous serial line]] [[peripheral]] produced by [[A
  4 KB (493 words) - 21:22, 17 October 2022
• SITS file system
  The '''ACCB''' flag bit signals the presence of access protection data, which is a series of three-byte blocks. The last block ha
  3 KB (429 words) - 19:21, 12 June 2023
• CD11 High-Speed Punched Card Reader Control Unit
  ...controller]] for the CR04 [[punched card]] reader. It used [[Direct Memory Access|DMA]] to transfer data.
  4 KB (563 words) - 01:45, 3 November 2022
• MX15-A Memory Bus Multiplexer
  ...ain memory]]. PDP-15 [[Central Processing Unit|CPU]]'s and [[Direct Memory Access|DMA]] [[peripheral]]s can be connected to the input ports. A PDP-15 CPU can The MX15-A allows the input ports access to the main memory on a priority basis; port 1 has the highest priority, an
  972 bytes (161 words) - 16:49, 1 December 2022
• GE-635
  ...ivities were handled by Input/Output Controller modules, similarly sharing access to the memory modules.
  2 KB (338 words) - 12:50, 5 January 2023
• GE-645
  | Controlled access || No || Yes || Yes ...es were handled by Input/Output Controller modules, which similarly shared access to the memory modules.
  4 KB (588 words) - 18:00, 12 January 2024
• X Window System
  ....) The streams connect the application to an X [[server]] which has direct access to the [[display]] being used.
  1 KB (172 words) - 23:01, 9 June 2023
• VAXstation 100 firmware notes
  ...nitially to be an optional add on, but later it was required. The BBA can access the [[frame buffer]] and has its own 256 by 16 bit scratchpad RAM.
  9 KB (1,261 words) - 08:50, 27 February 2024
• QBUS peripherals
  * [[DRV11-B Direct Memory Access Interface]] ** [[MSV11-L MOS Random-Access Memory|MSV11-L]] is covered on pp. 327-338
  4 KB (644 words) - 19:27, 16 February 2024
• Repairing early UNIX file systems
  ...ete blocks. ('raw' devices use the [[device controller]]'s [[Direct Memory Access|DMA]] capability to transfers block contents direct to and from [[buffer]]s
  10 KB (1,838 words) - 21:43, 12 June 2023
• The VMS-MicroVMS Merge
  ...command procedures? Thus, ADDUSER.COM (add a user account with appropriate Access Control List Identifiers and a user disk directory), BACKUSER.COM (backup u
  21 KB (3,330 words) - 03:40, 16 January 2024
• Local Area VAXcluster
  ...'boot server''' (providing boot services) and '''disk server''' (providing access to Cluster-wide mass storage). It was recommended to use dedicated [[VAXser
  2 KB (360 words) - 14:32, 13 August 2023
• TREK7
  CONNECTED BY A LONG NARROW ACCESS ROOM TO THE SECONDARY (OR Primary-Secondary Hull Access Boom/Access Boom Engine/Cooling Tubes
  64 KB (10,642 words) - 19:18, 1 February 2024
• Laser System Bus
  ...[multi-processor]]. The bus has special capabilities to support the shared access to memory required by such a system, including support for [[cache coherenc
  3 KB (396 words) - 01:44, 8 May 2024
• DMP11 Synchronous Controller
  ...ine]] [[peripheral|interface]] for the [[UNIBUS]]. It uses [[Direct Memory Access|DMA]] to transfer data to and from [[main memory]]. The DMP11 can operate i
  2 KB (277 words) - 00:21, 14 May 2023
• KS11 Memory Protection and Relocation option
  ...ddition to mapping addresses around, the KS11 also definitely limited user access to so-called [[UNIBUS|I/O page]] addresses.
  5 KB (754 words) - 17:58, 29 February 2024
• Tandy 1000 Series
  ...]] processor, 128k of [[Random Access Memory|RAM]], and no [[Direct Memory Access|DMA]] (although an expansion card was available the offered this and room t
  5 KB (781 words) - 09:42, 23 May 2023
• Running ITS (the Incompatible Timesharing System) on the KL-10
  ...xamined versus the type of cycle being requested by the processor. If a no access condition is indicated, a "page fault" is generated by the hardware. Otherw ...|| [This feature to be implemented by software on KL-10 using the regular access bit and the "Software" bit.]
  23 KB (3,961 words) - 17:58, 5 January 2024
• Tymshare
  ...are''' was an early computer services company, founded in 1966, which sold access to [[time-sharing]] systems (initially for engineers at aerospace companies * [http://archive.computerhistory.org/resources/access/text/2017/06/102717167-05-01-acc.pdf Oral History of Ann Hardy] - one of th
  977 bytes (136 words) - 17:45, 10 January 2024
• Installing ULTRIX-11 V1.0 on SIMH
  command can access the swap area, see `/dev/makefile'.
  33 KB (4,919 words) - 12:31, 21 June 2023
• DEC Unique Product Identifier
  061 | VAX PACKETNET SYSTEM INTERFACE ACCESS 0LW | DECSERVER NETWORK ACCESS SOFTWARE
  15 KB (1,675 words) - 09:17, 25 June 2023
• Installing and Configuring MicroVMS V4.0 on a MicroVAX I
  ** File Access Control List utilities
  53 KB (6,333 words) - 13:43, 19 July 2023
• PDP-9 control memory
  ...h gates input to the MB register, thus setting it to PC. SM starts memory access. ...MA/30<br>TI makes a check for indirect addressing. SM starts a new memory access to retrieve the instruction operand.
  11 KB (1,387 words) - 09:37, 13 August 2023
• RQDX1/RQDX2 MFM Disk & Floppy QBUS Controllers
  ...a RQDX1 containing ‘Rev 9.0' firmware it would no longer be possible to access it with a controller containing "Rev 8.0" firmware unless the Winchester di
  7 KB (1,107 words) - 05:04, 5 January 2024
• Interdata
  * the ' Selector Channel bus', which supported [[Direct Memory Access|DMA]]
  2 KB (228 words) - 14:31, 8 August 2023
• Microcontroller
  ...a [[Central Processing Unit|CPU]], [[Read-only memory|ROM]], and [[Random Access Memory|RAM]], along with all the support [[logic]] needed to create a funct
  515 bytes (73 words) - 01:57, 30 July 2023
• Sector interleaving
  '''Sector interleaving''' is a technique for speeding up access to sequential data on rotating magnetic media.
  3 KB (461 words) - 18:11, 21 January 2024
• RF30
  | average access time = 29 msec
  770 bytes (103 words) - 16:10, 18 August 2023
• RF71
  | average access time = 29 msec
  526 bytes (67 words) - 10:47, 18 August 2023
• Removable-pack disk
  ...platter(s), and a hatch in the cover allowed the heads to reach in to gain access to the platter(s).
  2 KB (394 words) - 14:17, 15 August 2023
• R80 Disk Drive
  <!-- | average access time = xx msec -->
  2 KB (306 words) - 11:10, 31 August 2023
• RF31
  | average access time = 23.6 msec
  488 bytes (54 words) - 10:46, 18 August 2023
• RF31F
  | average access time = 20.5 msec
  557 bytes (66 words) - 10:46, 18 August 2023
• RF31T
  | average access time = 13.1 msec
  555 bytes (66 words) - 10:46, 18 August 2023
• RF35
  | average access time = 15.1 msec ...uses a 50-pin DSSI interface and a 5-pin Molex power connector, providing access to 852 MB of storage. There are 7 platters, each with 2 heads, for a total
  2 KB (311 words) - 13:21, 20 November 2023
• RF36
  | average access time = 15.6 msec
  487 bytes (54 words) - 12:01, 18 August 2023
• RF72
  | average access time = 21.6 msec
  489 bytes (54 words) - 12:11, 18 August 2023
• RF73
  | average access time = 21.2 msec
  489 bytes (54 words) - 12:13, 18 August 2023
• RF74
  | average access time = 18.1 msec
  489 bytes (54 words) - 12:21, 18 August 2023
• EF51R Solid State Disk Drive
  | average access time = 0.25 msec
  1 KB (169 words) - 14:27, 2 December 2023
• EF52R Solid State Disk Drive
  | average access time = 0.25 msec
  1 KB (170 words) - 14:32, 2 December 2023
• EF53 Solid State Disk Drive
  | average access time = 0.25 msec
  1 KB (149 words) - 14:36, 2 December 2023
• HSD10 DSSI-to-SCSI Bus Adapter
  ...SSI buses to provide device access with no single points-of-failure in the access path. ...meters. It also can be used for device formatting and qualification and to access device information.
  5 KB (710 words) - 00:04, 13 January 2024
• PS/2 Model 60 Sales Brochure
  44Mb, 70Mb and optional 115Mb fixed disks provide ready-access storage for large files and applications, even elaborate data bases. ...options lets you connect Model 60 in a variety of local area networks and access the power of many larger systems.
  8 KB (1,167 words) - 19:03, 2 January 2024
• RC25 disk drive
  <!-- | minimum access time = --> | average access time = 30.5-45.5 msec
  2 KB (251 words) - 20:22, 23 April 2024
• ITS Internals Manual
  ...ach. Each page may individually be mapped to some backing store, and have access read/write bits set. Backing store is normally anonymous core memory or fi
  10 KB (1,580 words) - 14:00, 1 December 2023
• MIT UNIBUS XGP interface
  It used [[Direct Memory Access|DMA]] to transfer rasters from the PDP-11's [[main memory]] to the XGP. A r
  5 KB (869 words) - 13:30, 27 February 2024
• Edited Option/Module List
  ...st anything there, even the rarest code and devices, if you happen to have access to the right edition.
  1 KB (183 words) - 22:31, 1 October 2023
• List of Chaos application protocols
  * FILE &mdash; remote file system access; mainly for Lisp machines. * MLDEV &mdash; remote file system access; mainly for ITS.
  2 KB (259 words) - 17:41, 12 December 2023
• Common File System
  from more than one system to simultaneously access files. Any still access all files that do not depend on the down system
  53 KB (6,770 words) - 13:15, 16 November 2023
• DX10 Data Channel
  ...system application. The PDP-8's code is held in a normal PDP-8 4K [[Random Access Memory|RAM]], the 'control storage memory', and was loaded into the DX10 by
  3 KB (492 words) - 20:33, 12 February 2024
• Standard Tape Interconnect
  ...s]], SDB) with STI; the higher layer [[protocol]]s are adapted to [[random access]] storage needs. STI configurations are slightly more complex than SDI, as
  3 KB (392 words) - 04:13, 19 April 2024
• CompuServe
  ...founded in 1970 as a subsidiary of Golden United Life Insurance. They sold access to [[time-sharing]] systems, for which they used [[PDP-10]]'s heavily (init
  1 KB (142 words) - 08:22, 16 January 2024
• MIT AI memo 105
  Access to the additional teletypes is provided by five more bits
  2 KB (320 words) - 20:42, 10 January 2024
• CompuServe recollections
  that blocked access to the NISA applications (Forums, mail). Diagnosing
  5 KB (817 words) - 06:56, 20 February 2024
• SC-40
  ...[[microcode]]d, with 32K 80-bit [[word]]s of read/write microcode [[Random Access Memory|RAM]]; it had a 32K-word write-through [[cache]]. [[Main memory]] ([
  1 KB (194 words) - 18:51, 21 January 2024
• IBM I/O channel
  ...d transfer data to the [[main memory]] of the machine with [[Direct Memory Access|DMA]], and [[interrupt]] the [[Central Processing Unit|CPU]].
  5 KB (704 words) - 17:20, 9 April 2024
• Installing and Using the SIMH InfoServer150VXT
  X-terminal services Open disk access (any client) Open tape access (any client)
  9 KB (961 words) - 11:23, 28 January 2024
• CalComp Model 215 Disk Drive
  <!-- | average access time = 41.5 msec -->
  2 KB (229 words) - 18:18, 11 February 2024
• Trident disk drives
  <!-- | average access time = 41.5 msec -->
  2 KB (263 words) - 18:19, 11 February 2024
• MX10 Memory Multiplexer
  ...] allows several [[DF10 Data Channel]]s or [[DX10 Data Channel]]s to share access to a [[PDP-10 Memory Bus]], and thus, to the [[multi-port memory]] banks to
  788 bytes (124 words) - 01:09, 13 February 2024
• Intel 1103
  ...story.si.edu/collections/nmah_713496 Intel 1103 1K Bit pMOS Dynamic Random Access Memory (DRAM)] - the writeup may contain an error; it says "a one-transisto
  2 KB (235 words) - 16:41, 17 February 2024
• Memory Test Computer
  ...nough to hold an extended address, the MTC used [[bank switching]] to gain access to all of main memory.
  6 KB (932 words) - 22:10, 1 March 2024
• Automatic Computing Engine
  ...8-bit [[word]]s, it also had 5 4-word lines (the reduced size gave lower [[access time]]s), 4 2-word lines, and 7 1-word lines; the shorter ones had the role
  6 KB (855 words) - 03:53, 25 March 2024
• Pilot ACE
  ...ngth [[operand]]s), and 5 single-word lines (the reduced size gave lower [[access time]]s). The shorter ones had the role of [[register]]s in most computers.
  5 KB (812 words) - 03:52, 25 March 2024
• LGP-30
  ...ed around the track, with multiple read [[head]]s, so as to reduce their [[access time]].
  4 KB (607 words) - 22:47, 1 April 2024
• Bendix G-15
  ...nes had the role of [[register]]s in most computers, and came with lower [[access time]]s); to achieve that, the read and write [[head]]s were placed closer
  6 KB (870 words) - 22:44, 1 April 2024
• VAX 8200/8300 Revision Control
  | DHU11 | 16 Line Async Controller w/ DMA Access | Ref | | | | | |... | DMZ32 | 24 Line Async Controller w/ DMA Access | Ref | | | | | |...
  198 KB (5,881 words) - 23:03, 28 March 2024
• Packard Bell PB 250
  ...may be replaced by a shorter line, such as a 16-word line, for decreased [[access time]] (at the cost of a reduction in available space); line 0 is usually c
  7 KB (1,005 words) - 12:24, 2 April 2024
• Point-to-Point Protocol
  ...including [[SONET]], [[MPLS]], and [[Ethernet]] (where PPP is used to gain access to capabilities available under PPP, such as authentication).
  2 KB (295 words) - 17:48, 18 April 2024
• DR32 Device Interconnect
  ...] data path, along with an 8-bit path for control. It used [[Direct Memory Access]] to transfer blocks of data to and from [[main memory]] at rates of up to
  700 bytes (101 words) - 19:17, 14 May 2024

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