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DECnet
| DAP: Data Access Protocol<BR> ! Data link

17 KB (2,405 words) - 17:43, 13 January 2024
QBUS
...]] lines (to reduce the pin count), as opposed to the separate address and data lines of the UNIBUS. Another was that although it also supported 4 levels o ...write cycle); and interrupt cycles, in which a device causes the [[Central Processing Unit|CPU]] to perform an interrupt.

13 KB (2,043 words) - 23:27, 14 January 2024
UNIBUS
...S]], and thus supported several capabilities: the ability of the [[Central Processing Unit|CPU]] to read and write [[main memory]], and device [[register]]s; and The UNIBUS contained 16 data lines, and 18 [[address]] lines, as well as a number of control lines. The

13 KB (2,162 words) - 23:26, 14 January 2024
PDP-11/34
The [[Central Processing Unit|CPU]] came in two variants: the [[KD11-E CPU|KD11-E]] (M7265 and M7266 | 777711 || Source data

4 KB (536 words) - 19:28, 8 February 2024
PDP-11/20
...duced the [[UNIBUS]] as a universal path to connect together the [[Central Processing Unit|CPU]], [[main memory]] and [[peripheral|devices]]. ...pe puncher/reader. The front panel had lights and switches for address and data (the lights were not LED's).

6 KB (900 words) - 19:27, 31 December 2023
PDP-11/24
...Kbytes of EUB main memory, using a cross-connection path on the [[Central Processing Unit|CPU]] board. If no KT24 was present, the CPU detected its absence, and ...d devices. The two buses were not entirely separated: they shared a set of data lines, but each bus had a separate complete set of address lines. (The lowe

8 KB (1,395 words) - 23:37, 29 February 2024
PDP-11/44
...relying instead on the UNIBUS, and [[Extended UNIBUS|EUB]]. Its [[Central Processing Unit|CPU]], the [[KD11-Z CPU|KD11-Z]], was the last PDP-11 CPU to be made o ...All devices were attached to a semi-separate UNIBUS (it and the EUB shared data lines, but not [[address]] lines); [[Direct Memory Access|DMA]] devices cou

4 KB (584 words) - 23:42, 29 February 2024
PDP-11/45
...prior to 1976) or [[KB11-D CPU]] (later units) high-performance [[Central Processing Unit|CPUs]], implemented in [[SSI]] [[Schottky TTL]] logic. ...a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory

6 KB (895 words) - 23:52, 29 February 2024
PDP-11/70
...IBUS]] [[PDP-11]] system; it basically took the high-performance [[Central Processing Unit|CPU]] of the [[PDP-11/45]] (implemented in [[SSI]] [[Schottky TTL]] lo ...R-xx [[flat cable]]s; two for the [[address]] and control, and two for the data. They run from [[Berg connector]] headers on boards in the KB11 CPU's cache

5 KB (729 words) - 23:43, 29 February 2024
PDP-11 architecture
The [[Central Processing Unit|CPU]] had 8 [[general register|general purpose registers]]; the [[oper ...provide a variety of additional operand types, such as immediate (literal) data, absolute and relative addresses, and stack operations; very impressive on

13 KB (1,949 words) - 17:37, 29 February 2024
VAX-11/780
{{InfoboxVAX-Data The [[Central Processing Unit|CPU]] was the [[KA780 CPU]]. It could take an optional [[floating poin

8 KB (1,030 words) - 21:30, 25 April 2024
VAX-11/782
{{InfoboxVAX-Data ...ocessor|dual processor]] [[VAX]]; it had two [[KA780 CPU|KA780]] [[Central Processing Unit|CPUs]] connected to up to four [[MA780 Multiport Memory Option|MA780]]

3 KB (420 words) - 09:14, 15 July 2023
VAX-11/750
{{InfoboxVAX-Data ...ne which connected all the major functional units, including the [[Central Processing Unit|CPU]], [[main memory]], and I/O bus adapters, was the [[CPU/Memory Int

8 KB (1,063 words) - 14:49, 8 May 2024
PDP-8/E
...'PDP-8/F''' was a cost-reduced version of the -8/E with the same [[Central Processing Unit|CPU]], but only a single OMNIBUS [[backplane]]. The '''PDP-8/M''' is t * KD8-E [[OMNIBUS|Data Break]] Interface

4 KB (618 words) - 14:11, 14 July 2023
MOS Technology 6502
...ntroduced at around $25 it was the least expensive full-featured [[Central Processing Unit|CPU]] on the market by a considerable margin, costing less than one-si ...witch between 16 [[bank switching|banks]] of 64KB memory. The address bus, data bus, and R/W signal are tri-state, unlike the 6502, and the state is contro

8 KB (1,369 words) - 17:59, 25 June 2021
VAX-11/730
{{InfoboxVAX-Data ...way of extensive [[microcoding]] of the large architecture, the [[Central Processing Unit|CPU]] was shrunk to three [[DEC card form factor|hex]] boards. The mac

5 KB (708 words) - 12:22, 29 March 2023
Timeline of Norsk Data
* In July, Norsk Data-Elektronikk is founded. * The company changes name from "NORDATA Norsk Data-Elektronikk" to "Norsk Data A/S"

7 KB (950 words) - 12:59, 23 August 2016
NORD-10
| manufacturer = [[Norsk Data]] ...plications and for [[real-time]] multiprogram systems, produced by [[Norsk Data]]. It was introduced in 1973. The later follow up model, NORD-10/S, introdu

8 KB (1,313 words) - 13:52, 11 July 2023
MicroVAX I
{{InfoboxVAX-Data ...n|DEC]]. It used the [[QBUS]] as its primary [[bus]] between the [[Central Processing Unit|CPU]] (the [[KD32 CPU]]) and [[main memory]], the only [[VAX]] to do s

10 KB (1,543 words) - 02:27, 7 May 2024
MicroVAX II
{{InfoboxVAX-Data ...II''' was a small [[VAX]], with the [[KA630 CPU‎‎]] for its [[Central Processing Unit|CPU]]. Its [[bus]] between the CPU and [[main memory]] was a special b

5 KB (716 words) - 13:37, 6 May 2024
PDP-10
...the KS10 were available in [[multi-processor]] versions with two [[Central Processing Unit|CPUs]]. ...ided for the latter; it allowed peripherals to [[interrupt]] the [[Central Processing Unit|CPU]], and supported [[programmed I/O]] (including block transfers).

11 KB (1,640 words) - 20:59, 8 March 2024
PDP-8 architecture
...in one field could access data in the same field by direct addressing, or data in another field with indirect addressing. ...ory controller. The 62X1 instuction (CDF, Change Data Field) would set the data field to X. Similarly 62X2, CIF, set the instruction field, 62X3 set both.

22 KB (3,497 words) - 19:34, 29 November 2022
Bus
In computer [[architecture]], a '''bus''' is a subsystem that transfers data or power between computer components inside a computer or between computers ..., it might take too long for the program to check again, resulting in lost data. Engineers thus arranged for the peripherals to interrupt the CPU. The in

14 KB (2,170 words) - 05:09, 5 September 2019
VAX-11/785
{{InfoboxVAX-Data ...1/785''' was an upgraded version of the [[VAX-11/780|/780]]; its [[Central Processing Unit|CPUs]] used [[Advanced Schottky]] [[logic]]. A /780 could be upgraded

2 KB (193 words) - 04:26, 13 January 2024
LEO
* [http://www.cs.man.ac.uk/CCS/res/res02.htm#d Designing a computer for data processing] - personal memories from John Pinkerton, the principal engineer

2 KB (262 words) - 19:03, 18 March 2024
MicroVAX 3800/3900
{{InfoboxVAX-Data ...kplane. (The [[address space]] of the [[QBUS]] was limited to 4MB, and the data section is only 16 bits wide.)

3 KB (380 words) - 07:06, 31 January 2024
History of Zork
...programming languages like MDL (an important influence on modern Lisp) to data bases, electronic mail and artificially intelligent systems -- if only cent ...ms for keeping track of documents, handling electronic correspondence, and processing text. When Zork was added to the list of possibilities, Joel and Marc worke

38 KB (6,681 words) - 16:32, 19 December 2018
Incompatible Timesharing System
...al memory|paging]] [[hardware]] (which that generation of PDP-10 [[Central Processing Unit|CPU]] did not have). It later ran on the [[KL10]] and [[KS10]] models ...n units of either [[character]]s or [[word]]s (although an entire block of data could be transferred by a single [[system call]], if desired). All the usua

12 KB (1,926 words) - 21:29, 8 February 2024
ITS DDT Guide
command. It is so powerful that it can leave DDT's data bases ("kills") the current job. All the data in it is lost. The $J

171 KB (29,660 words) - 17:55, 28 December 2018
Top
immediately read for processing. See the section on the process (text, data, and stack), RES is the current

11 KB (1,552 words) - 13:03, 24 April 2024
TROPIX Manual
processing of devices already supported. ........ (and other data from computer) ............

91 KB (12,020 words) - 17:55, 13 August 2019
Operating system
...mple, operating systems provided [[file system]]s for users to store their data in. ...r could not interfere with another user, so protection of users (and their data, stored on disk) from each other became another function of the operating s

4 KB (608 words) - 15:04, 9 September 2022
VT100
...the VT100 into [[VT52]] mode (one of the VT series' features) because VT52 processing had less overhead.[1] ...and use every other measure to improve how fast the terminal could process data (see above).

4 KB (664 words) - 14:34, 11 August 2023
Intel 80386
...r '''i386''' for short) is the 4th generation [[microprocessor]] [[Central Processing Unit|CPU]] from [[Intel]] based on the 8088/8086 CPU. The 386 was a 32-bit ...could only address 16MB of RAM maximum. The 386SX also only could transfer data 16 bits at a time, so reading a 32-bit word took two reads. This basically

2 KB (372 words) - 01:23, 30 December 2021
J-11 chip set
...ls. It was implemented in two [[integrated circuit|chips]] ('Control' and 'Data') carried on a single 60-pin [[Dual Inline Package|DIP]] carrier. ...full [[PDP-11 Memory Management]] architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains bu

2 KB (242 words) - 23:19, 29 February 2024
Intel 4004
...-only memory|ROM]], [[Random Access Memory|RAM]] was only used for storing data, and this complicated the life of the [[programmer]] somewhat. ...by the Wxx instructions. (Also, the CM-RAM[0123] lines from the [[Central Processing Unit|processor]] chip are used to control "4002 RAM chips".)

5 KB (796 words) - 16:01, 14 July 2023
IBM AT
...y Standard Architecture|ISA]] slots, and the 'advanced' [[i286]] [[Central Processing Unit|CPU]]. The IBM AT unlike the [[IBM XT]] is fully 16 bit, with a 16-bit [[data bus]], 24-bit [[address bus]], and 16-bit ISA expansion bus. IBM had also

2 KB (396 words) - 00:41, 20 October 2018
COBOL
...arily found in [[mainframe]] environments, and is used in business [[batch processing]]. * data

3 KB (392 words) - 18:34, 14 January 2024
MSV11-J memory module
...-JC versions), it is really intended for use with a PMI-capable [[Central Processing Unit|CPU]], such as the [[KDJ11-B CPU|KDJ11-B]]. In systems such as the [[P The memory is arranged as 2 banks, each 16 data bits wide, with 6 additional bits for the ECC. One bank is used to hold [[w

8 KB (1,374 words) - 00:43, 30 July 2023
KA630 CPU
{{InfoboxVAXCPU-Data The '''KA630''' is the [[Central Processing Unit|CPU]] used in [[Digital Equipment Corporation|DEC]]'s [[MicroVAX II]].

2 KB (174 words) - 06:15, 28 June 2022
Starlink
...anticipated flood of data in digital form which would be generated by new data acquisition techniques. In April 1978, SRC set up a Panel on Astronomical Image and Data Processing under the chairmanship of Professor Mike Disney to ascertain the computing

1 KB (194 words) - 01:54, 20 December 2018
Intel 8086
...16-bit CPU, which means the internal [[data bus]], along with the external data bus. ...hile it retained the same addressing modes, and instructions, the external data bus was 8 bits wide. The 8088 was the primary CPU found in the [[IBM 5150|

1 KB (210 words) - 13:29, 3 November 2018
Intel 80186
...tral Processing Unit|CPU]]. It also exists in an 80188 variant (with 8-bit data bus, like the [[Intel 8088]]).

975 bytes (146 words) - 13:32, 3 November 2018
Real Programmers Don't Use Pascal
Real Programmers do List Processing in FORTRAN. ...ming language with all sorts of complications. The worst thing about fancy data types is that you have to declare them, and Real Programming Languages, as

22 KB (3,770 words) - 14:23, 25 August 2021
Linux 0.00
# The third is the system of data # Register all of the data, all point system, gdt Table 3

14 KB (1,991 words) - 01:23, 20 December 2018
DZ11 asynchronous serial line interface
...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line, using [[interrupt]]s. A 64-entry |Transmit Data Register || TDR || 760106

5 KB (730 words) - 02:26, 19 February 2023
Installing NetBSD 5.0.2 on the SIMH MicroVAX II
# Based on the maketape.c program and the maketape.data data file. i: Text Processing Tools No

8 KB (1,125 words) - 02:02, 18 November 2010
NetBSD 0.9 announcement
add delay loop to lpa and lpt drivers to allow data port fixed bug in ECHONL processing (andrew)

29 KB (4,794 words) - 18:15, 16 December 2018
DLV11-E asynchronous serial line interface
...ters for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]], or [[bootstrap|re-boot]] the system, when a '[[asynchronous ser

3 KB (489 words) - 01:18, 17 February 2023
DLV11-J asynchronous serial line interface
...r]]s for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h That line can be set to [[halt]] the [[Central Processing Unit|CPU]], or [[bootstrap|re-boot]] the system, when a '[[asynchronous ser

4 KB (684 words) - 01:20, 17 February 2023
DLV11 asynchronous serial line interface
...r]]s for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when a '[[asynchronous serial line|break]]' is seen.

2 KB (378 words) - 19:15, 7 July 2023
TPA-11/580
...open architecture member of the KFKI TPA-family. With a microcoded central processing unit, the speed and performance is due to its efficient instruction set and ...lates the 30-bit SBI addresses to 18-bit UNIBUS addresses, handles DMA and data buffering (The UBA does 4 UNIBUS-cycles on one SBI cycle).

4 KB (587 words) - 00:38, 2 January 2024
UNIX V6 memory layout
...y simple. The [[operating system]]'s [[kernel]] (both [[instruction]]s and data) permanently occupies low physical memory; [[process]]es reside above the k ...for one or two (see below) large block(s) containing the kernel's code and data; details of the kernel's address space and main memory layout are given bel

7 KB (1,161 words) - 15:20, 8 July 2023
KD11-E/EA microcode
...PU]] provide nice [[flow chart]]s for the [[microcode]] in these [[Central Processing Unit|CPUs]]; with one tiny exception, the microcode in the two is identical | 026 || 9-I || 322 || Fetch index data

31 KB (3,760 words) - 05:02, 5 November 2022
INTEL 80386 PROGRAMMER'S REFERENCE MANUAL
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, Genius, i, Œ, trademark. MDS(R) is a registered trademark of Mohawk Data Sciences

890 KB (107,817 words) - 03:20, 3 January 2024
IBM OS2 1.0 announcement
o Concurrent Processing of Multiple Applications of memory beyond 640KB for applications and data. End users will

50 KB (7,113 words) - 03:35, 17 December 2018
Inside OS/2
Library of Congress Cataloging in Publication Data British Cataloging in publication Data available

627 KB (92,395 words) - 03:42, 17 December 2018
LSI-11
...ped in the Fall of 1975, was DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPU]], introducing the [[QBUS]], and using the [[LSI-11 chip set]]. It ...component side facing the viewer) is [[KEV11]], μROM 1, μROM 0, Control, Data Path.

3 KB (411 words) - 22:06, 20 December 2023
LSI-11/2
...s]], using the same [[LSI-11 chip set‎]]. It contains only the [[Central Processing Unit|CPU]], and nothing else; it is otherwise identical in functionality to ...ips (from the handle end) is, in fact, [[KEV11]], Control, uROM 1, uROM 0, Data Path (per the KD11-HA print set); the order given in the Handbook is that f

2 KB (336 words) - 18:34, 19 July 2023
UNIX* System V and 4.1C BSD
void data type, and several bug fixes. The cc command including ged, a graphical editor, and numerous data

113 KB (13,419 words) - 02:06, 17 December 2018
MM11-L core memory
* G110 - [[DEC card form factor|hex-width]] memory control logic and data channels ...planes wired to hold one or more MM11-L sets, in addition to the [[Central Processing Unit|CPU]].

5 KB (841 words) - 07:14, 25 March 2022
Small Peripheral Controller
The appropriate UNIBUS signal lines ([[address]], data, etc) were thus wired to the appropriate rows/pins in SPC slots. Other pins ...] and [[PDP-11/34]], on the [[DD11-P backplane]] which holds the [[Central Processing Unit|CPU]] card(s), along with the [[KY11-LB Programmer's Console]] (which

5 KB (868 words) - 23:38, 9 April 2022
M9301 ROM
It used four 4-bit wide [[PROM]]s to hold the data. The board occupied [[address]]es 773000-773776 and 765000-765776; a config Other configuration switches controlled which address the [[Central Processing Unit|CPU]] jumped to on power on (a clever kludge, controlled by another co

9 KB (1,304 words) - 19:41, 7 December 2021
KL10
The [[Central Processing Unit|CPU]] had two main units, the 'E Box' ('Execution') and the 'M Box' (' ...alled; they connect to the E Bus (for control), and also to the C Bus (for data movement). The [[MASSBUS]] can be used to connect a variety of [[disk]] and

11 KB (1,737 words) - 13:06, 2 April 2024
KY11-LB Programmer's Console
...eripheral Controller|SPC]] slot in the same [[backplane]] as the [[Central Processing Unit|CPU]], and a 20-[[conductor]] [[flat cable]] which connected the two. ...d, a 6-digit [[Light Emitting Diode|LED]] display which showed address and data information, several individual indicator LEDs, and the following function

7 KB (1,114 words) - 20:56, 24 October 2022
FP11-B Floating-Point Processor
.../70]] computers ([[KB11-A CPU|KB11-A]] and [[KB11-B CPU|KB11-B]] [[Central Processing Unit|CPU]] variants thereof, respectively); it was the progenitor of the se * M8113 Exponent and Data Path

1 KB (201 words) - 02:17, 13 October 2022
FP11-C Floating-Point Processor
...uters (the later [[KB11-D CPU|KB11-D]] and [[KB11-C CPU|KB11-C]] [[Central Processing Unit|CPU]] variants thereof, respectively); it was [[program compatible]] w * M8129 Exponent and Data Path

1 KB (209 words) - 02:18, 13 October 2022
Private Memory Interconnect
...roduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit|CPU]] and a [[KTJ11-B UNIBUS adapter|KTJ11-B]] [[UNIBUS]] adapter to c ...[main memory]], PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte writes; ii) block mode, which can re

4 KB (731 words) - 17:11, 6 February 2024
KT11-B Paging Option
...although only a maximum of 64 KBytes is accessable (i.e. in the [[Central Processing Unit|CPU]]'s address space) at any one time. ...anently dedicating scarce memory space in the Exec's address space to such data, or ii) having to change a number of page table entries in the Exec mode pa

15 KB (2,571 words) - 22:23, 11 October 2022
PDP-11 Memory Management
The [[Central Processing Unit|CPU]] can be in one of three modes; 'Kernel', 'Supervisor', and 'User' An additional enhancement is that [[instruction]] and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called

9 KB (1,311 words) - 18:10, 2 July 2023
Virtual memory
...visible to to user as first-class objects, are supported in the [[Central Processing Unit|CPU]] (in the [[instruction]]s), etc; whereas pages are generally invi ...t size, measured in small units, is often stored in a field as part of the data which describes the segment to the CPU's hardware), whereas with variable p

5 KB (876 words) - 20:01, 22 January 2024
KA11 CPU
The '''KA11''' is the [[Central Processing Unit|CPU]] of the [[PDP-11/20]], the first [[PDP-11]]. It was the only PDP- * [[Data path|Data Paths]]

9 KB (1,356 words) - 23:10, 29 February 2024
KT11-B Technical Manual
...[[register]] names must be known, as well as the function of the [[Central Processing Unit|CPU]] and [[peripheral|device]] [[UNIBUS]]es, and also high-level inte [[Image:KT11-B_DataPaths.jpeg|450px|right|Main data paths]]

31 KB (4,983 words) - 18:22, 2 July 2023
KDJ11 CPUs
There are several single-board [[PDP-11]] [[Central Processing Unit|CPUs]] which all use the 'Jaws' [[J-11 chipset]]: ...even if that memory location is faulty - the CPU is getting the (correct) data from the cache.

3 KB (457 words) - 14:32, 21 February 2023
F-11 chip set
...P-11 architecture]]. It was used in the [[KDF11 CPUs]]. The main [[Central Processing Unit|CPU]] was implemented in two [[integrated circuit|chips]] (carried on ...although the KEF11-A is [[microcode]], there are enough pins for both the data [[bus]], and the microcode bus.)

2 KB (384 words) - 23:50, 28 March 2022
Central Processing Unit
The '''Central Processing Unit''', usually abbreviated as '''CPU''', or simply called a '''processor' Instructions include data-handling instructions (such as arithmetic and logical operations), and cont

1 KB (196 words) - 13:14, 5 November 2023
MASSBUS
...ion (the 'Control Bus'), and a [[synchronous]] data transfer section (the 'Data Bus'). The two sections operate completely independently. ...sing Unit|CPU]] access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bi

5 KB (729 words) - 21:36, 2 December 2023
LINC tape
Instructions in the LINC [[Central Processing Unit|CPU]] could seek to a given block, and then read or write multiple blo The tape contained timing and mark tracks along with three data tracks; the first two allowed not only the ability to re-write individual b

3 KB (519 words) - 02:13, 28 February 2024
LINC-8
...a [[Direct Memory Access|DMA]] peripheral to the PDP-8, using the PDP-8 [[data break]] mechanism). A combined [[front panel]] allowed control of both CPUs

2 KB (328 words) - 13:46, 11 July 2023
Core memory
...ch uses tiny rings of magnetic material ('cores', hence the name) to store data; magnetized in one direction, such a core represents a '1' [[bit]], and in ...location in main memory, the location can be read out, with the [[Central Processing Unit|CPU]] telling the memory to wait before the write-back, so the CPU can

8 KB (1,299 words) - 02:33, 4 March 2024
Main memory
'''Main memory''' refers to the [[memory]] from which the [[Central Processing Unit|CPU]] reads its [[instruction]]s as it [[execute]]s them; typically, a ...ata for immediate access by the CPU. Computers which keep instructions and data in the same memory are called 'von Neumann' [[architecture]]s; those which

2 KB (250 words) - 17:10, 11 September 2019
MK11 memory system
...erface boards (an M8158 address buffer board, and either an M8159 or M8164 data buffer board; the M8159 could only be used with 64KB memory modules, wherea [[Image:M8159MK11DBuf.jpg|thumb|250px|right|M8159 Data Buffer card (also with memory bus terminators)]]

8 KB (1,276 words) - 03:23, 6 February 2024
FIS floating point
As with the FP11 version, it was tightly integrated with the [[Central Processing Unit|CPU]], so that the CPU processed a mix of 'regular' and floating point ...e|regular PDP-11 registers]] as a pointer to load and store floating point data from/to memory; floating point values could only be stored in [[main memory

2 KB (355 words) - 17:49, 7 December 2021
Microcode
...the functionality needed to control the internal operation of a [[Central Processing Unit|CPU]]. ...f the CPU's internal [[hardware]] elements during that microcycle: routing data out of [[register]]s (including internal registers not visible to the progr

6 KB (853 words) - 14:25, 22 January 2024
KE11-F Floating Instruction Set
...uad]] board, the M7239, which plugs into a pre-wired slot in the [[Central Processing Unit|CPU]] [[backplane]]. ...but it also uses microcode stored on the KE11-E, to control registers and data paths elsewhere.

2 KB (246 words) - 02:34, 12 October 2022
DH11 asynchronous serial line interface
| DPR || OVR || FRM || PAR || colspan=4 | Line || colspan=8 | Data ...to the DH11 with a pair of BC08S cables, which carried the 'main' signals (data, etc - i.e. non-modem control); these cables were thus required for both 'l

10 KB (1,443 words) - 02:27, 19 February 2023
Non-Processor Request and Grant
...here; they are for a [[peripheral|device]] to gain control of the UNIBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle. ...name comes from the fact that the device cannot request that the [[Central Processing Unit|CPU]] perform any action (i.e. an [[interrupt]]) while the device has

1 KB (212 words) - 18:50, 6 July 2022
Programmed I/O
...Processing Unit|CPU]], using [[instruction]]s performed by the CPU to move data - as opposed to [[Direct Memory Access|DMA]], in which the [[peripheral|dev ...', in which the CPU has to regularly check the device to see if it needs a data transfer, and ii) '''interrupt-driven''', where the device causes an [[inte

1 KB (192 words) - 23:12, 20 October 2021
KD11-E CPU
[[Image:KD11-E M7265.jpg|250px|right|thumb|M7265 Data Paths card]] ...o [[DEC card form factor|hex]] [[printed circuit board]]s, the '''M7265''' Data Paths module and the '''M7266''' Control module. They plugged into a modifi

5 KB (791 words) - 02:23, 6 December 2022
KD11-EA CPU
[[Image:KD11-EA M8265.jpg|250px|right|thumb|M8265 Data Paths card]] ...o [[DEC card form factor|hex]] [[printed circuit board]]s, the '''M8265''' Data Paths module and the '''M8266''' Control module.

6 KB (1,045 words) - 22:47, 31 March 2022
Cache
...a larger collection of data, implemented in such a way that access to the data copy in the cache is faster than to that in the large, full store. ...d disk blocks are kept in main memory, and network caches, where copies of data read from the network are kept on the local machine's disk.

1 KB (251 words) - 00:58, 17 May 2023
NORD-TSS
...ing the summer holidays of 1971, Bo Lewendal (system programmer at [[Norsk Data]]) implemented the initial version. It was further developed throughout 197 * Has a [[batch processing]] system

1 KB (181 words) - 15:15, 9 September 2022
VAXstation II
{{InfoboxVAX-Data ...de); and the QBUS only for its [[input/output|I/O]] [[bus]]. Its [[Central Processing Unit|CPU]] was the [[MicroVAX II]]; the [[VCB01 Video Controller]] provided

2 KB (254 words) - 16:59, 15 January 2024
VAX 6000 Model 400
{{InfoboxVAX-Data ...ange member of the [[VAX 6000 series]] line, the first to provide [[vector processing]].

1 KB (151 words) - 15:01, 30 March 2023
VAX 8300
{{InfoboxVAX-Data The '''VAX 8200''' is a mid-range [[VAX]] dual-[[Central Processing Unit|CPU]] [[multi-processor]] system built around the [[VAX Bus Interconne

2 KB (210 words) - 23:10, 28 March 2024
VAX 8350
{{InfoboxVAX-Data ...s an improved version of the [[VAX 8300]] mid-range [[VAX]] dual-[[Central Processing Unit|CPU]] [[multi-processor]] system built around the [[VAX Bus Interconne

2 KB (201 words) - 23:11, 28 March 2024
VAX 8700
{{InfoboxVAX-Data The '''VAX 8700''' is a single-[[Central Processing Unit|CPU]] version of the [[VAX 8800]].

2 KB (189 words) - 04:28, 13 January 2024
VAX 8800
{{InfoboxVAX-Data The '''VAX 8800''' is a dual-[[Central Processing Unit|CPU]] version of the [[VAX 8700]].

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VAX 88x0
{{InfoboxVAX-Data ...computer models, the difference between them being the number of [[Central Processing Unit|CPUs]] installed in the basic cabinet:

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VAXstation 3520/3540
{{InfoboxVAX-Data ...around a unique [[bus]], the [[M-bus]], to which is attached the [[Central Processing Unit|CPU]], [[main memory]], a [[graphics]] adaptor, and an [[input/output|

3 KB (298 words) - 06:49, 17 April 2024
VAXstation 3200/3500
{{InfoboxVAX-Data ...]] bus. (The [[address space]] of the [[QBUS]] was limited to 4MB, and the data section is only 16 bits wide.)

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Relocatable binary
...code|binary]] [[instruction]]s and data 'understood' by a given [[Central Processing Unit|CPU]]. These modules, which can be easily modified to operate at any [ In addition to the instructions (in binary form) and data, a relocatable binary module contains other information, needed for the lin

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Binary
...level of essentially all computers. It can also refer to numbers or other data stored in this form. ...e low-level form of a computer program which the hardware in the [[Central Processing Unit|CPU]] can interpret directly.

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Secondary storage
...on it was not directly accessible to the [[Central Processing Unit|CPU]]; data in secondary storage generally had to be brought into main memory through a ...tape]], etc; these often were a bridge to prior non-electronic information-processing technologies (e.g. paper tape was used in [[teletype]]s).

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Complex Instruction Set Computer
...r''' (usually abbreviated to '''CISC''') is one from a school of [[Central Processing Unit|CPU]] [[architecture]] which was the default approach until the rise o ...t generation were performance limited by the speed at which they could get data and instructions from memory; and they were also often had limited address

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Architecture
...(both those visible to the [[programmer]], and internal registers); the [[data path]]s which connect them all together; and the control system (usually [[

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Stack
...rage which is used to temporarily hold data in a 'push-down' fashion; i.e. data can be '''pushed''' onto the stack, and then '''popped''' off of it (in the Modern [[Central Processing Unit|CPU]]s generally dedicate one [[register]] to be a [[stack pointer]],

931 bytes (164 words) - 16:20, 15 December 2018
Honeywell 6000 series
...he same: a [[tightly-coupled]] [[multi-processor]], with all the [[Central Processing Unit|CPUs]] sharing access to a collection of [[multi-port memory]] units. '''Note:''' ''The data below is generally sourced from Honeywell documentation, including marketin

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Instruction set
...to the repertoire of [[instruction]]s provided by any particular [[Central Processing Unit|CPU]] [[architecture]]. ...nstructions to be able to use a [[stack]] as the source or destination for data.

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Instruction
...allest unit of computation which a [[programmer]] can direct the [[Central Processing Unit|CPU]] to perform. ...U (e.g. add the contents of one [[register]] to another, or move a unit of data from a register, to main memory) - those items are instructions. (An instru

774 bytes (119 words) - 19:50, 3 June 2023
TOPS-10
...nded from the 'Monitor' OS used on the [[PDP-6]]. It provided both [[batch processing]] and [[time-sharing]] capabilities. TOPS-10 allowed programs to be separated into data and [[object code]] segments; the latter could be shared by all [[process]]

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RH11 MASSBUS controller
...1 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B'). ...t mode]]; in this mode, the PA and PB UNIBUS [[parity]] lines are used for data bits 16 and 17. The [[PDP-15]] and [[KS10]] made use of this capability, th

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KS10
...he main [[backplane]]), to which are attached the [[microcode]]d [[Central Processing Unit|CPU]], the [[main memory]] controller, and two or three [[UNIBUS]] ada ...internal bus; the address is transferred on one cycle, and the associated data on a following cycle.

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PDP-15
...between protected and un-protected memory, and two modes for the [[Central Processing Unit|CPU]]. A memory relocation option, the KT15, with a [[base and bounds] ...r 18-bit mode]], where the two [[parity]] lines were recycled into 2 extra data lines.

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RH70 MASSBUS controller
...[[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]). ...connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory (although the RH70's

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Program
* direction to move data from one place to another ...loaded into the [[main memory]] of the computer, from where the [[Central Processing Unit|CPU]] will fetch the individual [[instruction]]s of the program, and e

1 KB (201 words) - 11:55, 4 December 2023
PDP-9
| caption = PDP-9 at MIT Cognitive Information Processing Group ...nt Corporation|DEC]]'s fourth 18-bit computer, and the first DEC [[Central Processing Unit|CPU]] to use [[microcode]]. A little over 400 were built. It was basic

6 KB (801 words) - 22:14, 9 February 2024
IBM 709
...ddress]]ing, and [[channel]]s (called 'Data Synchronizers' at the time). A Data Synchronizer had two channels, to each of which could be attached a [[card ...ww-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP709.html 709 Data Processing System] - IBM Archive page

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IBM 7090
It was designed hurriedly to meet the requirements of Sylvania, the data processing subcontractor for the [[BMEWS]] missile warning [[radar]] network, which wa ...-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP7090.html 7090 Data Processing System] - IBM Archive page

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IBM 7094
...-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP7094.html 7094 Data Processing System] - IBM Archive page

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KK11-A Cache Memory
...e [[KD11-EA CPU]], one which added a high-speed [[cache]] to the [[Central Processing Unit|CPU]]. Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] addr

4 KB (553 words) - 02:36, 12 October 2022
UNICHANNEL 15 System
...acts as an I/O [[front end]], partially to offload the PDP-15's [[Central Processing Unit|CPU]], but also to allow PDP-15 systems access to devices which did no * A data channel between the two CPUs, which allows them to interrupt each other; th

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MX15-B Memory Multiplexer
The MX15-B allowed the PDP-11 (both the [[Central Processing Unit|CPU]], and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIB ...ers]] over it; they used the two UNIBUS [[parity]] lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 o

2 KB (314 words) - 00:35, 1 December 2022
M9312 ROM
...]] emulator over the console [[asynchronous serial line]], basic [[Central Processing Unit|CPU]] and [[main memory]] diagnostics, and the ability to [[bootstrap] The board used five 4-bit wide PROMs to hold the data; the DEC-supplied pre-programmed PROMs included the console emulator and di

7 KB (1,103 words) - 11:42, 3 April 2022
KD11-A CPU
The '''KD11-A''' [[PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/35]] and [[PDP-11/40]] was a multi-board [[micr * M7231 - Data Paths

4 KB (588 words) - 05:52, 8 April 2024
Able ENABLE
The ENABLE took an incoming UNIBUS segment, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] [[peripheral controller|dev ...rt [[PDP-11 Memory Management|Split I+D]], whether it is an instruction or data fetch.

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DL10 PDP-11 Data Link
The '''DL10 PDP-11 Data Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communica ...]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, b

5 KB (664 words) - 17:27, 7 November 2023
TM10 Magnetic Tape Control
...F10 Data Channel]] for data transfers, to reduce the load on the [[Central Processing Unit|CPU]].

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Rubin 10-11 interface
...s) did not have access to the KA10's memory (unlike with the [[DL10 PDP-11 Data Link|DL10]] and [[DTE20 Ten-Eleven Interface|DTE20]], similar devices). ...particular alignment of the window on the UNIBUS side was necessary; the [[data path]] for the [[address]] must have contained an [[adder]].)

3 KB (402 words) - 17:01, 22 March 2024
PDP-5
...boards (equal to the [[word]] length of the machine) formed the [[Central Processing Unit|CPU]]. To minimize the initial basic cost, it had an [[input/output|I/ ...data.computerhistory.org/brochures/dec.pdp-5.1964.102646094.pdf Programmed Data Processor-5] - marketing brochure from DEC

2 KB (360 words) - 20:03, 7 February 2024
KD11-B CPU
The '''KD11-B''' [[PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/05]] and [[PDP-11/10]] was a two-board [[microc [[Image:KD11-B M7260C.jpg|250px|right|thumb|A KD11-B M7260 Data Paths card, etch revision C]]

11 KB (1,726 words) - 21:07, 2 July 2023
Peripheral
...[[secondary storage]] which is permanently accessible; some other form of data storage, intended for off-line storage (e.g. [[magnetic tape]]); or communi ...]] or [[Direct Memory Access|DMA]] to get data in and out of the [[Central Processing Unit|CPU]] and/or [[main memory]], and [[interrupt]]s to get the CPU to pay

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Word
...n computer architecture, a word may denote data processed by the [[Central Processing Unit|CPU]], an instruction, an address, or the unit by which [[main memory]

957 bytes (151 words) - 11:41, 11 August 2023
IBM 704
...ww-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP704.html 704 Data Processing System] - IBM Archive page

2 KB (278 words) - 02:11, 9 August 2022
Front end
.... saving [[register]] contents) can be significant, particularly for small data items, so avoiding bothering the main CPU with this cost (often larger in a ...n CPU, a technique used in the PPUs of the [[CDC 6600]], the [[DL10 PDP-11 Data Link|DL10]]-[[PDP-11]] combination of the [[PDP-10]] family, etc.

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NORD-OPS
...running under SINTRAN, providing the user with the possibility of [[batch processing]] [[job]]s and / or activities in "conversational mode" while they use SINT [[Category: Norsk Data Software]]

1 KB (171 words) - 15:06, 9 September 2022
Xerox Alto
The Alto's 16-bit-wide [[Central Processing Unit|CPU]] was [[microcode]]d (which resulted in it being called the machin ...RAM]] microcode memory. (The basic ROM microcode more or less emulated a [[Data General]] [[Nova]].) Some Alto IIs supported a second 1KW of PROM microcode

6 KB (863 words) - 22:39, 3 October 2023
Multi-port memory
...e physically separately connected to multiple clients (typically [[Central Processing Unit|CPUs]], [[channel]]s, [[Direct Memory Access|DMA]] [[device controller ...ntention ever happens (since each port has its own private copy of all the data). If more than one port can write, however, contention may arise in the wri

1 KB (192 words) - 16:36, 15 December 2018
UNIVAC I
...ords each (to reduce access times over fewer, larger lines). The [[Central Processing Unit|CPU]] operated in digit-serial mode (i.e. a digit at a time), to match ...nly [[input/output]] devices were [[magnetic tape]] units, the 'UNISERVO'. Data could be transferred to and from tape with off-line [[peripheral]]s which a

2 KB (319 words) - 01:12, 12 July 2023
Punched card
...[[secondary storage|data storage]] in the early period of computer usage. Data was stored in them by the presence, or absence, of holes punched in pre-det ...became a world-wide colossus before World War II on its dominance of card processing.

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KB11-A CPU
The '''KB11-A''' [[Central Processing Unit|CPU]] is the earlier CPU for the [[PDP-11/45]]. The optional [[FP11-B * M8100 Data and Address Paths

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KB11-D CPU
The '''KB11-D''' [[Central Processing Unit|CPU]] is the later [[Central Processing Unit|CPU]] for the [[PDP-11/45]]; it differed from the earlier [[KB11-A CPU * M8100 Data and Address Paths

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Multi-processor
A '''multi-processor''' is a system with more than one [[Central Processing Unit|CPU]]. There are a tremendous range of designs, from 'tightly-coupled' * MIMD - 'multiple instruction streams, multiple data sets'

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KE11-E Extended Instruction Set
...hex]] board, the M7238, which plugs into a pre-wired slot in the [[Central Processing Unit|CPU]] [[backplane]], and also connects up to the basic CPU's [[microco ...which produces an additional 24 bits width of microcode (to control the [[data path]]s and [[register]]s on the M7238), but also provides 44 bits of micro

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FP11-F Floating-Point Processor
...card (the '''M7093'''), which plugs into a dedicated slot in the [[Central Processing Unit|CPU]]'s [[backplane]]. The CPU and the FPP interact over two [[tri-state]] [[data path]]s, one for data, and another for the [[microcode]] [[Program Counter|PC]]. The CPU and FPP

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KD11-Z CPU
The '''KD11-Z CPU''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/44]]; the terminal letter code 'Z' was a tip to ...devices were attached to a semi-separate [[UNIBUS]] (it and the EUB shared data lines, but not address lines); [[Direct Memory Access|DMA]] devices could g

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KB11-B CPU
The '''KB11-B''' [[Central Processing Unit|CPU]] is the earlier CPU for the [[PDP-11/70]]. It is heavily based on * M8130 Data Paths

3 KB (456 words) - 21:08, 2 July 2023
Bit-mapped display
...'s main [[bus]], with the display memory directly visible to the [[Central Processing Unit|CPU]] as [[main memory]]. Due to the intimate relationship with the re | 1971 || [[Data Disc]] || [[Stanford Artificial Intelligence Laboratory|Stanford AI Lab]] |

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National Semiconductor NS405 and NS455 Terminal Management Processor
...] provide complete [[video terminal]] functionality, including a [[Central Processing Unit|CPU]] which can use either internal or external [[read-only memory|ROM ...itsavers.trailing-edge.com/pdf/zentec/Zentec_ADM3_Retrofit/NS405.pdf NS405 data sheet]

1 KB (164 words) - 04:42, 27 February 2023
Memory interleaving
...erently has a much longer cycle time since it has destructive readout; the data has to be written back before a read cycle can complete.)

2 KB (349 words) - 23:12, 29 July 2023
Expression
...is then used in some way - perhaps saved in [[main memory]] or a [[Central Processing Unit|CPU]] [[register]] for use later in the [[program]].

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OMNIBUS
...rammed I/O]], in which the [[Central Processing Unit|CPU]] reads or writes data to the [[device controller]]; * '''''Data break transfers''''', the PDP-8 term for [[Direct Memory Access|DMA]].

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PDP-8/L
...] in the [[PDP-8 family|PDP-8]] line; it apparently had the same [[Central Processing Unit|CPU]] as the -8/I. ...differed from the MC-8/I of the PDP-8/I in that the Instruction Field and Data Field [[register]]s were only one bit wide, not three bits as in the MC-8/I

2 KB (298 words) - 14:11, 14 July 2023
Intel 80486
...or]]s, the 4th generation in that line. It is basically the same [[Central Processing Unit|CPU]] as the 386, but includes an 8K byte [[cache]], and optionally (i ...he two used in the 386, speeding it up considerably. Its [[main memory]] [[data bus]] is 32 [[bit]]s wide, the same as the 386.`

1 KB (219 words) - 13:26, 3 November 2018
FPP8/A Floating Point Processor
...|CPU]], but used [[Direct Memory Access|DMA]] for its [[instruction]]s and data.

680 bytes (114 words) - 22:25, 22 November 2019
Intel Pentium
Externally, it is functionally the same [[Central Processing Unit|CPU]] as the 486, but includes a number of internal improvements to in ...[[cache]]s, one each for [[object code|code]] and data, so that [[loop]]s processing large [[array]]s will not empty the cache.

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Co-processor
...s in tandem with the main CPU, under its direction, to perform some of the processing functions of the system.

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Job
...it of work for a computer; e.g. an [[application]] together with its input data, often for a [[batch operating system]]. ...at contained a program (typically in [[object code]] form), along with the data to be processed by that program. The operator would pass the job to the com

1 KB (235 words) - 02:25, 11 September 2022
CDC 6600
| manufacturer=[[Control Data Corporation]] ...was an influential early (1964) [[mainframe]] computer; the dual-[[Central Processing Unit|CPU]] version of the 6600 was denominated as a '''CDC 6700'''. It is g

6 KB (789 words) - 17:26, 22 January 2024
IBM 7030 Stretch
...o introduced the concept of the 8-[[bit]] [[byte]], although the [[Central Processing Unit|CPU]] could [[address]] individual bits. ...uhaha.com/~eric/retrocomputing/ibm/stretch/ IBM Stretch (aka IBM 7030 Data Processing System)]

3 KB (467 words) - 16:37, 11 January 2024
IBM 650
The '''IBM 650''' (formally the '''Type 650 Magnetic Drum Data-Processing Machine''') was one of [[International Business Machines|IBM]]'s first comp ...serial, not bit-, though). The two internal [[register]]s in the [[Central Processing Unit|CPU]] (a 10-digit 'distributor', and a 20-digit [[accumulator]]) used

4 KB (620 words) - 21:08, 18 March 2024
IBM 7070
...though), and had three internal word-length [[register]]s in the [[Central Processing Unit|CPU]]; they used [[magnetic field|magnetic]] [[memory]]. Decimal [[flo ...[[magnetic tape drive]]s could be connected to a 7070, via two separate [[data channel]]s; the 729II could read 15,000 characters per second, the 729IV co

3 KB (478 words) - 14:49, 9 April 2024
Address bus
...ny buses contain an address bus as part of their structure, along with a [[data bus]], etc.

370 bytes (58 words) - 04:31, 13 December 2018
Data bus
...ing Unit|CPU]], but possibly a [[device controller]], Many buses contain a data bus as part of their structure, along with a [[address bus]], etc.

365 bytes (59 words) - 04:32, 13 December 2018
Superscalar
A '''superscalar''' [[Central Processing Unit|CPU]] [[architecture]] is one which has more than one [[logic]] unit w ...er renaming]] is used to allow the later one to start as soon as its input data is available, but using a different physical register.

1 KB (229 words) - 22:56, 9 September 2021
Channel
...put/output|I/O]] operations, off-loading that work from the main [[Central Processing Unit|CPU]]; they are connected to [[peripheral]]s, and usually have direct ...nsiderably from manufacturer to manufacturer: for instance, the Peripheral Processing Units of the [[CDC 6600]] are effectively channels, but they are essentiall

1 KB (205 words) - 17:18, 9 April 2024
DF10 Data Channel
...to it) to the system's [[PDP-10 I/O Bus|I/O bus]], to allow the [[Central Processing Unit|CPU]] to control it. * Discard data

2 KB (390 words) - 07:32, 6 September 2023
FPF11 floating point processor
...(the M8188) which plugs into the [[backplane]] slot next to the [[Central Processing Unit|CPU]] board. It can be plugged into either a [[UNIBUS]] or [[QBUS]] b ...is nothing for it to do; e.g. when the FPF11 does not need it to [[fetch]] data from, or [[store]] it in, [[main memory]].

2 KB (383 words) - 02:31, 12 October 2022
LSI-11 chip set
The '''LSI-11 chip set''' [[Central Processing Unit|CPU]] [[integrated circuit|chip]] set is used in the [[LSI-11 CPUs]] - The chip set consists of a [[data path]] chip, a control chip, and two or three [[microcode]] [[Read-only mem

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KY11-A Programmer's Console
...in [[main memory]], and start, [[halt]] and [[single-step]] the [[Central Processing Unit|CPU]]; it also displays substantial amount of information as the machi The 'Address' and 'Data' indicator arrays display memory [[address]]es and data.

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Register renaming
...''' is a technique used in the implementation of [[superscalar]] [[Central Processing Unit|processors]], particularly in those using [[out-of-order execution]], ...sters, more than can be named in the instructions - use of these keeps the data in the CPU, where it is quickly accessible. Register renaming is however ne

1 KB (191 words) - 16:05, 15 December 2018
UNIX V6 dump analysis
...omething happens it can't recover from; or after [[halt]]ing the [[Central Processing Unit|CPU]]. ...nd the per-process kernel [[stack]]), as well as the user's data (both the data area, and the user stack) in a single contiguous block in main memory, and

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KD11-K CPU
The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management * Data Path (M7874)

4 KB (536 words) - 12:34, 11 October 2022
FP11-E Floating Point Processor
which mounted in slots 8-11 of the [[Central Processing Unit|CPU]]'s [[backplane]]. The main CPU can detect the presence of the FP1 ..., it connected directly to the CPU and is controlled by it; unidirectional data buses are provided to move information (including instructions) from the CP

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MD10 core memory
...stem, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

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MA10 core memory
...ystem, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

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MB10 core memory
...stem, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

881 bytes (134 words) - 13:53, 2 August 2023
ME10 core memory
...ystem, one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

1 KB (181 words) - 13:55, 2 August 2023
MF10 core memory
...least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

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MG10 core memory
...least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

2 KB (342 words) - 12:33, 5 November 2023
MH10 core memory
...least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.

3 KB (407 words) - 12:40, 5 November 2023
MF20 MOS memory
...ovided to protect the memory contents; an MF20 44-[[bit]] word contains 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MF20 can be

2 KB (278 words) - 15:50, 24 October 2022
MG20 MOS memory
<!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[ ...G20 almost certainly shared the MF20's 44-[[bit]] word, which contained 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MG20 could

2 KB (355 words) - 15:49, 24 October 2022
RH20 MASSBUS controller
...ory of the system, to allow it to use [[Direct Memory Access|DMA]] to move data directly from devices to main memory, without needing CPU intervention.

2 KB (294 words) - 12:59, 12 November 2023
DLV11-F asynchronous serial line interface
...ters for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when a '[[asynchronous serial line|break]]' is seen; it can also

3 KB (469 words) - 01:19, 17 February 2023
KE11-A Extended Arithmetic Element
...hift operations. As a UNIBUS peripheral, not integrated into the [[Central Processing Unit|CPU]], it was also usable with other models, e.g. the [[PDP-11/05]] an ...20-777336. The operation to be performed is selected by the register which data is written to. Registers which hold results are readable, but many of the o

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Able UNIVERTER
...y the low-level details differ. (E.g. the UNIBUS carries [[address]]es and data on separate [[conductor|lines]], whereas the QBUS carries them both on a se ...s that the [[bus grant|bus arbiter]], and the interrupt-fielding [[Central Processing Unit|processor]], be on the QBUS. The UNIVERTER does not have to be at the

2 KB (251 words) - 18:32, 5 December 2022
Bus Arbitration on the Unibus and QBUS
...(sometimes multiple processors) and peripheral devices together and allows data transfers between the various components. As a general rule, one and only o ...asserts BBSY and becomes the bus master. The requesting device now can run data transfer bus cycles. When it's done, the requesting device negates SACK and

21 KB (3,685 words) - 04:35, 28 November 2023
DM11-BB Modem Control Option
...be connected to [[modem]]s. It could be set to [[interrupt]] the [[Central Processing Unit|CPU]] when a modem control line (Ring, Carrier, etc) changed state. *DTR - Data Terminal Ready; allow modem to enter data mode

7 KB (975 words) - 04:15, 18 February 2023
KA650 CPU
{{InfoboxVAXCPU-Data The '''KA650''' is the [[Central Processing Unit|CPU]] used in several [[Digital Equipment Corporation|DEC]] [[MicroVAX

3 KB (369 words) - 08:32, 12 September 2023
KA650 Main Memory System
...[[KA650 CPU]], and later [[KA655 CPU]]. It is split between the [[Central Processing Unit|CPU]] card, which contains the main memory controller, and a number of ...XA21), which are used as bank selection when using 256kxX DRAM chips. The data lines are carried to the RAM cards through a 50 conductor [[flat cable|ribb

42 KB (5,491 words) - 12:55, 7 May 2024
Three cycle data break
...ss storage]]) to [[main memory]], used on a number of [[List of Programmed Data Processors|early DEC computers]]. ...update the transfer address, and finally store or retrieve the actual I/O data word.

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DZV11 asynchronous serial line interface
...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line. |Transmit Data Register || TDR || 760106

5 KB (684 words) - 11:36, 17 February 2023
DZQ11 asynchronous serial line interface
...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line. |Transmit Data Register || TDR || 760106

5 KB (677 words) - 11:45, 17 February 2023
Tandberg TDV 1200
| manufacturer = Tandberg Data ...' [[video terminal]] was produced by [[Tandberg Data]] and sold by [[Norsk Data]] (ND) as product number 110140. It was also known as ND Display Terminal 1

3 KB (421 words) - 22:10, 9 May 2021
Bank switching
Rather, it is most commonly found in machines whose [[Central Processing Unit|CPU]] [[architecture]] provides a limited [[address space]] - less tha ...ferent bank. (In some systems, instructions are fetched from one bank, and data from a potentially different bank.)

3 KB (468 words) - 15:36, 7 November 2021
PDP-8 Memory Extension units
...fetch]]es. (The DF is only used for ''indirect'' data word fetches; direct data fetches - i.e. in the same page as the instruction - use the IF.) They coul ...occurs; and the Break Field Register, a 3 bit wide register used during [[data break]] [[Direct Memory Access|DMA]] operations, to select the field those

4 KB (614 words) - 21:02, 7 August 2022
Pure code
...iety of reasons (including not interacting well with a number of [[Central Processing Unit|CPU]] optimizations), so essentially all object code is now pure code. ...the [[instruction]]s to be segregated (in the [[address space]]) from the data, since the latter would presumably differ among the instances of the progra

956 bytes (155 words) - 14:46, 12 June 2021
DA10 Twelve- and Eighteen-Bit Computer Interface
...20 In/Out Bus Controller]] to provide an I/O bus. Unlike the [[DL10 PDP-11 Data Link|DL10]], it didn't use [[Direct Memory Access|DMA]], just [[programmed The DA10 is used in the DC68A Data Communication System, which uses a [[PDP-8/I]].

3 KB (442 words) - 14:51, 7 March 2023
Shift register
...rpose of the shift register. For instance, a shift register in a [[Central Processing Unit|CPU]], used for arithmetic purposes, would typically be both loaded an Another common use of a shift register is to take data being sent between two subsystems in serial form, using a single [[conducto

1 KB (236 words) - 20:43, 4 August 2021
Serial
...essing where one [[bit]] is handled at a time, with successive bits in any data item (such as a [[word]]) being handled in later time slots. ...and the [[arithmetic logic unit|ALU]] in a [[serial computer]]'s [[Central Processing Unit|CPU]], which would have only a single-bit adder, and to add two number

688 bytes (116 words) - 23:28, 6 August 2021
DV11 Communications Multiplexer
...[[flat cable]]s connect the main unit to each distribution panel (two for data and [[clock]], two for modem control.). ...different 16-[[bit]] [[instruction]]s (BRANCH A, BRANCH B, ALU OP, RAM OP, DATA XFR, NPR OP, SET/CLR OP, BCC OP), and an [[arithmetic logic unit|ALU]] buil

6 KB (823 words) - 04:24, 18 February 2023
International Network Working Group
...was given a formal home in the [[International Federation for Information Processing]], as IFIP Working Group 6.1 - Computer Communication.

1 KB (185 words) - 18:10, 20 January 2024
UNIBUS Device Addresses
[[Central Processing Unit|CPU]] [[register]]s marked as "[[PDP-11/73|11/73]]" also appear in the | 777732 || Diagnostic Controller Data (11/84)

7 KB (927 words) - 11:26, 12 November 2021
Alto-1822 Interface
...[[Central Processing Unit|CPU]] bus, and used custom [[microcode]] to move data to and from [[main memory]]. It was [[full-duplex]], but included no [[buff

3 KB (443 words) - 14:59, 21 May 2023
DMA Request and Grant
...there; they are for a [[peripheral|device]] to gain control of the QBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle. The [[Central Processing Unit|CPU]] may not perform ''any'' action (i.e. an [[interrupt]]) while the

1 KB (190 words) - 04:01, 21 November 2021
Datapoint 2200
The base unit included a [[CPU|Central Processing Unit]], a small amount of [[main memory]], two digital cassette [[magnetic ...have an 8-bit [[operation code]], and an optional single byte of immediate data, or two bytes of [[address]].

5 KB (814 words) - 20:05, 4 June 2023
DW780 Unibus Adapter
* M8272 - UBA Map and Data Path (UMD) ...a custom 6-slot [[backplane]] (normally mounted next to the main [[Central Processing Unit|CPU]] backplane). 2 slots (on the back of the backplane) are used to h

2 KB (251 words) - 00:57, 7 May 2024
KA780 CPU
The '''KA780 CPU''' was the [[Central Processing Unit|CPU]] for the [[VAX-11/780]]. | 13 || M8229 || DAP || Data Path

2 KB (259 words) - 00:08, 3 January 2022
MA780 Multiport Memory Option
* in each connected [[Central Processing Unit|CPU]] (between 2 and 4), an '''MA780-C Port Interface''', held in anot | 11 || M8212 || MDT || Memory Data Paths

3 KB (479 words) - 15:45, 7 April 2024
Synchronous Backplane Interconnect
...s the high-speed bus which connected the major functional units ([[Central Processing Unit|CPU]], [[main memory]], [[Input/output|I/O]] adapters, etc), in early ...me other operation might use some of the slots before the one in which the data is returned.

3 KB (410 words) - 01:46, 8 May 2024
KK11-B Cache Memory
...D11-Z CPU]] of the [[PDP-11/44]], a high-speed [[cache]] for the [[Central Processing Unit|CPU]]. Each cache entry was 30 bits wide, containing two data bytes; also a tag field for cache entries, 9 bits wide (covering [[Extended

3 KB (501 words) - 16:27, 6 February 2024
KY11-J Programmer's Console
...in [[main memory]], and start, [[halt]] and [[single-step]] the [[Central Processing Unit|CPU]]. The 'Address/Data' indicator array display memory [[address]]es and data. The 'Run' light indicates that the CPU is [[execute|executing]] [[instruct

2 KB (372 words) - 18:05, 25 January 2022
KDJ11-D CPU
...KDJ11-D/S''' in the later variant (below), is the third [[QBUS]] [[Central Processing Unit|CPU]] card using the [[J-11 chip set]] of the [[PDP-11]] of the [[KDJ1 ...f the logic into two [[gate array]]s (DC7063 for control, and DC7064 for [[data path]]s), which made room for up to 1.5MB of memory.

3 KB (529 words) - 12:01, 15 August 2022
DEC Semiconductor Chips
| NVAX Central Processing Unit [[#ref_25|[25]]] | F-11 Data [[#ref_1|[1]]][[#ref_30|[30]]]

36 KB (3,420 words) - 05:36, 5 November 2022
M7259 Parity Control Module
...is thus not supported for MM11-L/MM11-U units in a [[PDP-11/05]] [[Central Processing Unit|CPU]] backplane. On a read cycle, when the memory unit has put the data on the UNIBUS, it asserts that signal; on seeing it, the M7259 then generat

4 KB (621 words) - 22:21, 6 July 2022
KA750 CPU
The '''KA750 CPU''' was the [[Central Processing Unit|CPU]] of the [[VAX-11/750]]. It was a [[synchronous]] [[microcode]]d d * L0002 Data Path Module (DPM) - arithmetical and logical functions, micro-sequencer

3 KB (437 words) - 01:40, 14 June 2022
KDF11-U CPU pinout
...mi-separate [[UNIBUS]], and [[Extended UNIBUS]] used between the [[Central Processing Unit|CPU]] and [[main memory]]; others are part of the connection between t | FN1 || K12-D4 || DATA TERM RDY 2

8 KB (1,587 words) - 16:14, 6 February 2024
CPU/Memory Interconnect
...he main [[bus]] which connects the main sub-systems (such as the [[Central Processing Unit|CPU]] and [[main memory]], as well as [[input/output|I/O]] adapters) i ...ns of the CMI are to do priority arbitration for use of the bus, and carry data between the sub-systems, as well as carrying [[interrupt]]s. It is also use

3 KB (391 words) - 01:41, 8 May 2024
VAX Bus Interconnect
...nnects all the main sub-systems, such as [[main memory]] and the [[Central Processing Unit|CPU]] (including [[multi-processor]]s); in the others, it is only used ...ully distributed among all the nodes, with no 'master' node), and transfer data between the sub-systems, as well as carrying [[interrupt]]s. It is also use

3 KB (438 words) - 01:46, 8 May 2024
VAXELN
Such applications include the typical scientific and industrial data processing situations in which the computer's operation has to be precisely synchroniz

2 KB (349 words) - 22:22, 28 June 2022
VAXstation I
{{InfoboxVAX-Data ...r both its [[main memory]] and [[input/output|I/O]] [[bus]]. Its [[Central Processing Unit|CPU]] was the [[MicroVAX I]]; the [[VCB01 Video Controller]] provided

1 KB (147 words) - 17:19, 15 January 2024
KD32 CPU
[[File:M7135_DATAPATH.JPG|300px|thumb|rightt|M7135 MicroVAX I Data Path Module (DAP)]] The '''KD32''' (also called the '''KA610''') was the [[Central Processing Unit|CPU]] in the [[MicroVAX I]], and its [[workstation]] form, the [[VAXst

2 KB (298 words) - 06:29, 28 June 2022
Subroutine call
...l [[instruction]] in the [[object code]]; on systems which interpolate a [[data network]] between components of the system, there are [[protocol]]s which i

463 bytes (63 words) - 18:41, 6 February 2023
VAX-11/780 & VAX-11/782 Revision Control
5.2 KA780 11780 CENTRAL PROCESSING UNIT cases excessive data lates occur with the RM03 disks or line drop

70 KB (7,782 words) - 14:04, 2 July 2022
KA785 CPU
The '''KA785 CPU''' was the [[Central Processing Unit|CPU]] for the [[VAX-11/785]]. | 13 || M7471 || DAP || Data Path

2 KB (205 words) - 16:36, 1 July 2022
Symbolics
...-volume custom [[Central Processing Unit|CPU]] of the LISP machine (tagged data types; [[garbage collection]]) left them unable to keep up.

2 KB (213 words) - 10:20, 10 January 2024
KA730 CPU
* Data Path (DAP - M8390) ...data-handling bus called the Port Bus (again with a 32 bit data path, for data only) runs from the DAP module to the FPA and the [[RB730 Integrated Disk C

2 KB (234 words) - 00:54, 6 July 2022
Installing, Configuring, and Testing A VMS V4.7 Local Area VAXcluster on SIMH
...ources as user and application data disks, printers, and distributed batch processing facilities. ...r resources, though they may also sometimes provide disk serving and batch processing resources.

112 KB (13,727 words) - 18:09, 30 January 2024
Standard Disk Interconnect
...DSA), used with [[PDP-11]]s and with [[VAX]] single and multiple [[Central Processing Unit|CPU]] systems. ...haracteristics, direct its mechanical operation, store data on or retrieve data from it, and recognize and recover from error conditions.

4 KB (512 words) - 15:29, 29 December 2023
HSC50 Hierarchical Storage Controller
...n support a total of six disk and/or tape data channels. Each one of these data channels accommodates four cabling bulkhead ports. Maximum disk configurati * Disk Data Channel (L0108-YA or K.sdi) - Supports up to four SDI disk drives (for exam

9 KB (1,370 words) - 23:47, 28 December 2023
Berkeley Computer Corporation
...System|BTSS]] [[time-sharing]] system, running on a modified [[Scientific Data Systems|SDS]] [[SDS 930|930]] (eventually resulting in SDS offering the [[S ...done, in 1970, their funding (from the [[mainframe]] leasing company Data Processing Financial & General (DPF&G)) was cut off, and BCC went bankrupt.

1 KB (163 words) - 19:18, 10 June 2023
Standard I/O library
...the overhead of doing a whole [[system call]] for each byte will make the processing of the file a lot slower than using this library. Using this library also a ...he standard library uses [[pointer]]s to [[structure]]s which hold all the data related to a particular file.

2 KB (272 words) - 11:22, 1 January 2023
GE-645
...can be used to hold a segment number; an instruction can specify that its data address is formed from the segment number in an ABR, and an offset in the i ...: it was a [[tightly-coupled]] [[multi-processor]], with all the [[Central Processing Unit|CPUs]] sharing access to a collection of [[multi-port memory]] modules

4 KB (588 words) - 18:00, 12 January 2024
General Electric
...]]s; and it was also involved in commercial data processing (notably check processing for the Bank of America). GE eventually decided to leave the computer busin ...onics Division, in Syracuse, New York. When GE entered the commercial data processing field, Phoenix was chosen as the location for the Computer Department, whic

4 KB (669 words) - 20:53, 12 January 2024
Standard Drive Bus
...DSA), used with [[PDP-11]]s and with [[VAX]] single and multiple [[Central Processing Unit|CPU]] systems. ...nal carriers, using small-diameter [[coaxial cable]]s; two for moving user data, commands, and responses between drive and controller, and two for continuo

2 KB (301 words) - 12:59, 19 April 2024
Local Area VAXcluster
...ources as user and application data disks, printers, and distributed batch processing facilities. ...r resources, though they may also sometimes provide disk serving and batch processing resources. If satellite nodes are equipped with disks, they may, for enhanc

2 KB (360 words) - 14:32, 13 August 2023
Laser System Bus
It supports multiple [[Central Processing Unit|processors]] and multiple [[main memory]] memory modules; a single [[I ...connected to the bus to every slot in the [[backplane]]). Arbitration and data transfers use logically separate divisions of the bus, so they can occur in

3 KB (396 words) - 01:44, 8 May 2024
Datapoint
...al Corporation''') was a ground-breaking business computerized information processing company. The 2200 had an even bigger indirect impact, though: its [[Central Processing Unit|CPU]] was initially intended to be a custom [[integrated circuit|chip]

3 KB (379 words) - 04:59, 2 June 2023
Running ITS (the Incompatible Timesharing System) on the KL-10
...mode" or "KL-10 paging" mode [[hardware]] mechanism in the KL-10 [[Central Processing Unit|processor]]. ...appens in the case of a "normal [[instruction]]" when all required mapping data is found within the hardware pager memories.

23 KB (3,961 words) - 17:58, 5 January 2024
KY11-D Programmer's Console
...in [[main memory]], and start, [[halt]] and [[single-step]] the [[Central Processing Unit|CPU]]. The 'Address/Data' indicator array display memory [[address]]es and data. The 'Run' light indicates that the CPU is [[execute|executing]] [[instruct

2 KB (397 words) - 20:32, 30 June 2023
KY11-P programmer's console
...in [[main memory]], and start, [[halt]] and [[single-step]] the [[Central Processing Unit|CPU]]. If the CPU has the DCS (Diagnostic Control Store), it can be ac The display shows memory [[address]]es and data. The 'Run' light indicates that the CPU is [[execute|executing]] [[instruct

2 KB (312 words) - 17:39, 5 July 2023
PDP-9 control memory
* Data channel requests will similarly "boost" the address. ...CI gates input to the MB and PC registers. SM starts a new memory cycle. Processing enters the fetch phase at CMA 21.

11 KB (1,387 words) - 09:37, 13 August 2023
Sector interleaving
'''Sector interleaving''' is a technique for speeding up access to sequential data on rotating magnetic media. ...the sectors had been arranged with one immediately after the other on the data media, the following sector would already have started when the software we

3 KB (461 words) - 18:11, 21 January 2024
PS/2 Model 60 Sales Brochure
...microprocessor and 1Mb memory are the right combination to cut through big processing jobs in a hurry. And this model offers large — and expandable — fixed-d .... So you can use it for such important tasks as spreadsheet processing and data base management.

8 KB (1,167 words) - 19:03, 2 January 2024
VT36 Color Graphics Display Control System
...nitoring as they occur. Being microprocessor-based, the VT36 minimises the processing load on the host computer. Up to four VT36s can, therefore, be configured o ...VT36 significantly reduces the load on the host CPU, freeing it for other processing.

16 KB (2,398 words) - 12:26, 27 February 2024
Common File System
12.1.7 "Cluster Data Gathering" them are for transmitting data and the other two are for receiving

53 KB (6,770 words) - 13:15, 16 November 2023
MCA25 KL Cache/Paging Upgrade
...grade''' was an optional improvement for the [[KL10]] [[PDP-10]] [[Central Processing Unit|CPU]]; it replaced the earlier [[MCA20 Cache]]. It increased the size * 4 x M856 Cache Data

2 KB (342 words) - 18:10, 14 November 2023
MCA20 Cache
...f [[instruction]]s and [[operand]]s, etc, for the early [[KL10]] [[Central Processing Unit|CPU]]. (It was later replaced by the improved [[MCA25 KL Cache/Paging * 4 x M8521 - Cache Data

3 KB (490 words) - 18:09, 14 November 2023
ITS 138
...rmedal's 1986 book "The Tomorrow Makers". In 2023, MIT Museum staff began processing the listing, and volunteers transcribed it to machine readable files. The * DEC Type 555 "[[DECtape|microtapes]]" with data channel.

5 KB (675 words) - 08:28, 19 January 2024

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