Difference between revisions of "FP11-C Floating-Point Processor"

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The '''FP11-C''' was a [[Floating point processor|FPP]] used in the [[PDP-11/45]] and [[PDP-11/70]] computers (KB11-D and KB11-C CPU variants thereof, respectively); it operated in parallel with the main processor, so that two instructions (one floating point, one regular) could be processed at the same time.
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The '''FP11-C''' was a [[Floating point processor|FPP]] used in the [[PDP-11/45]] and [[PDP-11/70]] computers (the later KB11-D and KB11-C CPU variants thereof, respectively); it was program-compatible with the [[FP11-B Floating-Point Processor]], which was the progenitor of the semi-standard [[FP11 floating point]] used in many later [[PDP-11]]s.
  
Like the [[FP11-B]], it supported short (32 bit) and long (64 bit) floating point numbers; both forms used an 8 bit exponent (in 'excess 0200' notation, giving an exponent range of +127. to -128.), a sign bit, and the remaining bits were the fractional part. A state bit controlled whether the FP11-C operated in short or long mode.
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Like the FP11-B, it operated in parallel with the main processor, so that two instructions (one floating point, one regular) could be processed at the same time; unlike the FP11-B, it used an internal clock which is synchronized to the basic CPU's clock.  
 
 
The FP11-C contained 6 internal registers, each capable of holding either a short or long floating point value.
 
  
 
==Implementation==
 
==Implementation==
  
The FP11-C used a clock which is synchronized to the basic CPU's clock. It plugged into special pre-wired slots in the CPU's [[backplane]], and included the following boards:
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It plugged into special pre-wired slots in the CPU's [[backplane]], and included the following boards:
  
 
* M8128 ROM and ROM Control
 
* M8128 ROM and ROM Control
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{{PDP-11}}
 
{{PDP-11}}
  
[[Category:DEC processors]]
 
 
[[Category:UNIBUS processors]]
 
[[Category:UNIBUS processors]]

Revision as of 15:04, 18 September 2016

The FP11-C was a FPP used in the PDP-11/45 and PDP-11/70 computers (the later KB11-D and KB11-C CPU variants thereof, respectively); it was program-compatible with the FP11-B Floating-Point Processor, which was the progenitor of the semi-standard FP11 floating point used in many later PDP-11s.

Like the FP11-B, it operated in parallel with the main processor, so that two instructions (one floating point, one regular) could be processed at the same time; unlike the FP11-B, it used an internal clock which is synchronized to the basic CPU's clock.

Implementation

It plugged into special pre-wired slots in the CPU's backplane, and included the following boards:

  • M8128 ROM and ROM Control
  • M8129 Exponent and Data Path
  • M8126 Fraction Data Path - High Order
  • M8127 Fraction Data Path - Low Order