|Year Introduced:||June 1972|
|Word Size:||16 bit|
|Physical Address Size:||18 bit|
|Virtual Address Size:||16 bit|
The difference between the two CPUs was whether they worked with the FP11-B or FP11-C FPP. The FP11 floating point was optional, as was the KT11-C Memory Management Unit (the first implementation of the full PDP-11 Memory Management).
The PDP-11/50 and PDP-11/55 were systems which used the exact same processor, but were sold pre-configured with the special high-speed MS11 Semiconductor Memory System (specific to the PDP-11/45), using 350 nsec MOS or 300 nsec bipolar memory, respectively.
The MS11 high-speed memory was dual-ported: one port went to a special high-speed bus to the CPU (called the Fastbus), which was implemented as part of the CPU's backplane; the other went to a second UNIBUS (the 'B' UNIBUS).
That UNIBUS could either be connected to a second PDP-11 (creating a multi-processor PDP-11 system), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that DMA devices on that UNIBUS could do I/O to the fast memory, which was accessible only from the CPU when the two UNIBUSes were split.
Note that if the system contained a dual-UNIBUS RH11 MASSBUS controller, devices attached to that could reach the fast memory in a split-UNIBUS system if the RH11's second UNIBUS was attached to the 'B' UNIBUS, giving them a high-speed path to the memory on which there was no contention with the CPU.
The high-speed memory could be configured in two semi-independent banks, each with its own dual-ported M8110 (later M8120) Semiconductor Memory Control module.
When the -11/45's CPU went to do a memory cycle, it started cycles on both the FastBus and the 'A' UNIBUS; if that address was in an MS11, the MS11's controller indicated that it had it, over a special FastBus line. The UNIBUS cycle would then be abandoned before the CPU asserted MSYN.
A number of products from Able Computer made use of the FastBus; the Able CACHE/45 (which provided a cache), and the Able SCAT/45 (which was an MS11 equivalent which could support up to 256 Kbytes of memory).
Quoting: Introduced two years after the PDP-11/20, in June 1972. The KB11 was a faster, microcoded CPU built with SSI/MSI (Small/Medium Scale Integration) components. The machine had two different buses: one was a UNIBUS with 18-bit addressing, the other was a fast CPU-memory interconnect. It also introduced split I/D (Instruction/Data) spaces (UNIX used this; the DEC operating systems did not), an MMU (Memory Management Unit) option, an optional FPU (Floating Point Unit). The maximal ammount of memory was 128 Kwords.
The cycle time of the PDP-11/45 with bipolar memory (max. 8 KW!) was 300 ns, MOS memories (max. 32 KW) were 450 ns, and core was 980 ns - but without memory management! The MMU added 90 ns to the cycle time.
The PDP-11/50 was basically the same machine with different memory. The PDP-11/55 (KB11-D CPU) used the modified CPU of the PDP-11/70, where the cache was left out (instead the memory was the faster bipolar memory). It also had the kernel/supervisor/user operating modes seen on the PDP-11/70, but only had a 18-bit addressing range. It was the fastest of the "classic" PDP-11 CPU's when measured by the cycle times.
- PDP-11/45, 11/50 and 11/55 system user's manual (EK-1145-OP-001)
- PDP-11/45 maintenance reference manual (DEC-11-HMRMA-A-D)
- PDP-11/45, 11/50 and 11/55 system maintenance manual (EK-11045-MM-007)
- PDP-11/45 /70 Maintenance Course handout book
- PDP-11/45 system engineering drawings (June 1974)
- PDP-11/45 system engineering drawings (June 1976)
- 11/55 Vol. 1 Field Maintenance Print Set (MP00039)
|v • d • e PDP-11 Computers and Peripherals|
|UNIBUS PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 • PDP-11/05 • PDP-11/10 • PDP-11/34 • PDP-11/04 • PDP-11/44 • PDP-11/60 • PDP-11/24 • PDP-11/84 • PDP-11/94|