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- ...'''DASD''', is [[International Business Machines|IBM]] jargon for [[random access]] [[secondary storage]] devices, such as [[floppy disk]]s, hard [[disk]]s,277 bytes (37 words) - 14:50, 25 August 2021
- '''Random Access Memory''' (often given as '''RAM''') is slang term for a computer's [[main ...disk]] [[secondary storage]] (although technically disks are also [[random access]] - unlike, say, [[magnetic tape]] secondary storage).457 bytes (64 words) - 13:25, 20 November 2023
- '''Direct Memory Access''', usually abbreviated as '''DMA''', refers to a now-very-common technique ...e. In the second, the memory has multiple ports, and the device has direct access to the memory via one of the ports.751 bytes (125 words) - 23:08, 20 October 2021
- #Redirect [[Random Access Memory]]34 bytes (4 words) - 05:21, 12 November 2016
- ...ion''' (often given as the acronym, '''CSMA-CD''') is a way of controlling access to a [[Local area network|LAN]] using a [[broadcast]] bus (i.e. a shared br1 KB (181 words) - 16:10, 7 June 2022
- #Redirect [[Direct Memory Access]]34 bytes (4 words) - 16:43, 14 May 2018
- ...etimes '''response time''') is the time period between the start of a read access cycle, and the point in time when the data is returned to the requestor. ...n the request arrives, that can delay the memory's response - and thus the access time for that particular cycle.690 bytes (113 words) - 02:11, 20 September 2022
- ...go to disparate [[address]]es without significant delays; in '''sequential access''' memories, only successive operations to following locations can be done834 bytes (110 words) - 01:56, 24 December 2018
- #Redirect [[Random access]]27 bytes (3 words) - 15:52, 10 October 2018
- ...[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.3 KB (380 words) - 03:54, 10 June 2020
- [[Access time]] is 210-230 nsec for reads, and 90-120 nsec for writes; [[cycle time]6 KB (926 words) - 14:10, 22 September 2022
- 4 KB (600 words) - 21:23, 2 July 2023
- ...[[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device. It was a single [[DEC card form fa .../www.bitsavers.org/pdf/dec/unibus/EK-DR11W-UG-004.pdf DR11-W Direct Memory Access Interface Module User's Guide] (EK-DR11W-UG-004)5 KB (746 words) - 17:48, 2 December 2021
- '''Media Access Control Addresses''' (usually shortened to the acronymic form, '''MAC Addre1 KB (162 words) - 01:15, 11 July 2022
- #Redirect [[Media Access Control Address]]42 bytes (5 words) - 01:15, 11 July 2022
- 33 bytes (3 words) - 22:14, 24 March 2024
Page text matches
- ...int-to-point links only. Introduction of file transfer (FAL), remote file access (DAP), task-to-task programming interfaces and network management features. ...ntroduction of adaptive routing capability, downline loading (MOP), record access, a network management architecture, and gateways to other types of networks17 KB (2,405 words) - 17:43, 13 January 2024
- ...ude [[DIGITAL Command Language|DCL]] as a choice for the CLI, giving users access to essentially the same command language used in [[RSX-11]] and, later, [[V14 KB (2,134 words) - 16:06, 3 May 2023
- ...memory|ROM]] (1 Kword) and a small amount of [[core memory|core]] [[Random Access Memory|RAM]] (128 words). It is not clear if any of these machines were eve2 KB (233 words) - 19:22, 8 February 2024
- | access-date=September 26, 20162 KB (243 words) - 18:25, 13 January 2024
- ...and [[peripheral controller]]s through read-write cycles, [[Direct Memory Access|DMA]], and [[interrupt]]s, as well as in much of the low-level detail, such13 KB (2,043 words) - 23:27, 14 January 2024
- ...nd device [[register]]s; and the ability for devices to do [[Direct Memory Access|DMA]] transfers to memory, and to [[interrupt]] the CPU.13 KB (2,162 words) - 23:26, 14 January 2024
- ==Register access==4 KB (536 words) - 19:28, 8 February 2024
- | memory speed = [[MM11-E and MM1-F core memories|MM11-E]]: 500 nsec [[access time]]<br> 1.2 μsec [[cycle time]]6 KB (900 words) - 19:27, 31 December 2023
- ...UNIBUS and the EUB for access to all of memory for UNIBUS [[Direct Memory Access|DMA]] devices; without it, the UNIBUS [[address space]] was statically mapp ...ath for addressing information to flow from the UNIBUS to the EUB, for DMA access to main memory by devices.8 KB (1,395 words) - 23:37, 29 February 2024
- ...ut not [[address]] lines); [[Direct Memory Access|DMA]] devices could gain access to the memory via a [[UNIBUS map]] which connected the two, and mapped UNIB4 KB (584 words) - 23:42, 29 February 2024
- ...em), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that [[Direct Memory Access|DMA]] devices on that UNIBUS could do [[input/output|I/O]] to the fast memo6 KB (895 words) - 23:52, 29 February 2024
- ...[[main memory]] via a new Main Memory Bus, and changes to the CPU to allow access to that much memory * A [[UNIBUS map]] to allow devices on the UNIBUS access to all of that memory5 KB (729 words) - 23:43, 29 February 2024
- | average access time = 49 msec3 KB (492 words) - 00:27, 15 August 2023
- The name of bit 6 has changed slightly from the RK11-C to the -D ("Access Ready" to "R/W/S Ready"), but it seems to be basically the same functionali14 KB (2,038 words) - 23:04, 13 September 2023
- ...dge [[disk]] [[drive]]s. All data transfers are done using [[Direct Memory Access|DMA]]. Data is protected with a [[hardware]]-generated and checked [[error-4 KB (563 words) - 13:33, 26 February 2023
- | minimum access time = 258 16 μsec | average access time = 16.9 msec (60 Hz [[alternating current|AC]] power)<br>20.3 msec (501 KB (212 words) - 22:14, 14 August 2023
- | average access time = 67.5 msec Some later drives have access panels which can be removed to gain to the solenoid. On older ones, one has8 KB (1,357 words) - 16:33, 18 August 2023
- ...ous later models added various instructions for Processor Status Word (PS) access, maintenance, etc.13 KB (1,949 words) - 17:37, 29 February 2024
- | average access time = 70 msec7 KB (1,170 words) - 00:30, 15 August 2023
- ...05 drives. It used the [[single cycle data break]] form of [[Direct Memory Access|DMA]] to transfer data directly to [[main memory]]. It uses blocks of 256 w712 bytes (111 words) - 18:25, 29 April 2021
- Memory: Includes 16K bytes of Random Access Memory (RAM)2 KB (326 words) - 03:10, 23 May 2023
- * [[ACCESS]], an on-line query system, allowing user-friendly access to a data-base via interactive terminals.7 KB (950 words) - 12:59, 23 August 2016
- ...had a priority from 0 to 3. A program on a lower ring was never allowed to access the pages on a higher ring. Programs which ran on rings 2 and 3 could use t ...rupt priority level|interrupt priority]] of the device. In [[Direct Memory Access|DMA]] transfers the device would send a "REQUEST". The CPU would answer wit8 KB (1,313 words) - 13:52, 11 July 2023
- For [[Direct Memory Access|DMA]], [[mass storage]] peripherals connected directly to memories (PDP-10 * [https://archive.computerhistory.org/resources/access/text/2023/07/102737607-05-19-acc.pdf DECsystem-10 Technical Summary/DECSYST11 KB (1,640 words) - 20:59, 8 March 2024
- ...s used. With this clever combination, a program running in one field could access data in the same field by direct addressing, or data in another field with All supported [[Direct Memory Access|DMA]], called "data break" in the PDP-8's. There were two types.22 KB (3,497 words) - 19:34, 29 November 2022
- ...computers began to share memory between several CPUs. On these computers, access to the bus had to be prioritized, as well. The classic, simple way to prioritize interrupts or bus access was with a [[daisy chain]].14 KB (2,170 words) - 05:09, 5 September 2019
- hackers interested in operating systems and 386's with access to minix. >happening. However, for the time being I am without FTP access so I don't28 KB (4,805 words) - 18:01, 29 February 2024
- ...the drum to fetch it. And another 16ms if a complete turn was necessary to access the data address, y-addr. From this it is clear how a dedicated programmer4 KB (647 words) - 20:59, 18 March 2024
- ...tion on system state. DCL includes [[Conditional statement|IF-THEN-ELSE]], access to all the [[Record Management Services|RMS]] file types including stream,6 KB (913 words) - 18:07, 16 December 2018
- ...chnique sometimes used on computers whose [[main memory]] was not [[random access]], but sequential (such as [[delay line]]- and [[drum]]-based memory).2 KB (229 words) - 22:13, 24 March 2024
- Otherwise, from BASIC, you access the monitor by running: === Single Address Memory Access ===2 KB (282 words) - 16:55, 16 December 2018
- ...OM on the [[Central Processing Unit|CPU]] board, which prevents multi-user access to these computers.3 KB (380 words) - 07:06, 31 January 2024
- ...Level 8505 - Tur(n)key Level 4- Version 1.00, update 08 - Explains how to access the publicly available online demo system as well as a link to the download1 KB (209 words) - 13:43, 1 November 2021
- ...direct download on sourceforge.net]. To use uudeocde to decode it, simply access the [[boot42|article]], and copy the contents of the quoted text (the begin13 KB (2,064 words) - 18:04, 5 August 2017
- /usr/chris/dungeon/dtext.dat Text file in random access-format21 KB (3,303 words) - 07:30, 6 September 2023
- ...uploaded a copy onto this wiki in uuencoded format. To decode it, simply access the [[boot42|article]], and copy the contents of the quoted text (the begin14 KB (2,318 words) - 06:15, 1 September 2018
- *Access to Host OS filesystems using BetaDOS or MiNT native XFS driver1 KB (155 words) - 10:09, 16 May 2013
- ...with each other, and to use each other's machines. In those halcyon days, access was unrestricted; you could get on from any machine connected to the net, o .... jargon) could somehow be brought to more people. But very few people had access to the large computers that could run Zork. More and more people were begin38 KB (6,681 words) - 16:32, 19 December 2018
- ...] release. IBM had done their best to tune OS/2 to run in 4MB of [[Random Access Memory|RAM]] on a 386SX CPU. Warp also included the 'bonus pack' which inc These are the ones I currently have access to, or directly know about:22 KB (3,500 words) - 04:39, 13 January 2024
- ...'''DASD''', is [[International Business Machines|IBM]] jargon for [[random access]] [[secondary storage]] devices, such as [[floppy disk]]s, hard [[disk]]s,277 bytes (37 words) - 14:50, 25 August 2021
- are available immediately through SunSoft. An early access release of10 KB (1,426 words) - 17:55, 13 January 2024
- Unlike [[Random Access Memory|RAM]], ROMs cannot be written to. At one point, ROMs are also typica1 KB (179 words) - 12:58, 26 April 2022
- They're not totally open access; you have to register with DDJ to get all of them. However, there is this:6 KB (725 words) - 17:44, 13 January 2024
- The [[User Datagram Protocol]] is used to provide access to an un-reliable datagram service, for [[application]]s which don't need t5 KB (753 words) - 23:02, 29 January 2024
- ...e [[S-100]] type machines, is that unlike the [[IBM PC]] the S-100's could access the full megabyte of RAM. According to Tim Patterson this feature was used2 KB (250 words) - 14:07, 22 May 2023
- the program to access remote mailboxes "xpop3" and 4: Access to file systems FAT-32 for more than 4 GB.91 KB (12,020 words) - 17:55, 13 August 2019
- * Separate [[access control list]]s for each 'file'9 KB (1,331 words) - 17:05, 7 March 2024
- With MS-DOS installed and able to access a CD-ROM, you will need a blank floppy image, in addition to either an ISO If you have access to [[Visual C++ 1.1]] or the [[Windows NT 3.1 SDK]] you'll be in luck as yo5 KB (947 words) - 11:21, 9 June 2023
- ...ts (ones that use TCP/IP are better!), sound settings and of course CD-ROM access. I'll update these topics in the future.2 KB (433 words) - 05:16, 3 May 2015
- ...3.5 and 3.51 include an update to NT 3.1's NTFS driver to allow NT 3.1 to access an NTFS partition that has been mounted by NT 3.5 or later.15 KB (2,465 words) - 20:47, 13 January 2024
- access as well as for the audio capabilities indicated. The following modems are supported for use with Remote Access Service.144 KB (18,526 words) - 03:17, 17 December 2018
- ...me fun, Murray teased David that David's new Windows 286 (Windows 2.x with access to the 64-KB HMA) was basically a joke. What one really should do was to ge With Windows now running in protected mode, that meant that people would have access to more memory (albeit in 64k chunks as both the 386 & 286 kept the 286's m10 KB (1,619 words) - 20:45, 13 January 2024
- ...a 3000 used ZIP RAM instead of DIP, at the time allowing for faster memory access. However the industry at large would shun the [[ZIP]] chip, and instead mo ...lemented a bit blitter in hardware. The original version of the chip could access 512KB of 'chip RAM', the fat Angus could up that to 1024KB, and the fatter13 KB (2,120 words) - 00:41, 17 December 2018
- ...rdware, emulates the intended function the real-mode program was trying to access, or terminates the real-mode program if it is trying to do something that c ...even checked the drive but simply will not permit the real-mode program to access it. Also, the V86 monitor can do things like map [[main memory]] [[virtual4 KB (680 words) - 18:10, 20 February 2024
- ...Basic were known for needing line numbers, and it allowed direct hardware access via PEEK,POKE keywords. Many of these programs were NOT portable, as the h2 KB (358 words) - 04:39, 25 January 2023
- ...lowing for a flat memory space where the entire 4GB of accessible [[Random Access Memory|RAM]] could be accessed without [[segment]]ation. The 386 was introd2 KB (372 words) - 01:23, 30 December 2021
- ...it had a 24-bit [[address bus]] to allow access for up to 16MB of [[Random Access Memory|RAM]], and a [[virtual address|virtual]] [[address space]] of 1GB. T2 KB (320 words) - 13:35, 3 November 2018
- access as well as for the audio capabilities indicated. The following modems are supported for use with Remote Access Service, and279 KB (34,581 words) - 03:21, 17 December 2018
- devices meant to be used for teletype access should (to should be taken to change the access modes (chmod(1)) on24 KB (3,883 words) - 10:33, 6 March 2023
- ...central processor is executing in the context of a process, there are four access privilege modes (user, supervisor, executive, kernel), each with its own st ...e-access port becomes the console. A terminal connected through the remote-access port can halt the central processor, boot it, diagnose it, etc.49 KB (7,745 words) - 14:29, 6 May 2023
- ...lso gives each DOS application up to 640 K random access memory (RAM) plus access to expanded memory through use of a built-in LIM software driver.5 KB (748 words) - 18:06, 13 January 2024
- with. As far as I know, both SCSI and ST506 access are integrated on the A2090a to J5. However, others have noted the SCSI access circuitry as136 KB (31,870 words) - 21:08, 14 January 2024
- ...though effectively 2MHz there as well due to [[wait state]]s to give video access to system bus. In C64 compatibility mode the 8502 dropped down to 1MHz.2 KB (244 words) - 14:26, 25 October 2018
- ...system generation to the front of the system namelist for quicker access. devices meant to be used for teletype access should (to avoid confusion, no other reason) be named /dev/ttyX, where X42 KB (6,834 words) - 03:01, 17 January 2023
- .... It could only [[execute]] code out of [[Read-only memory|ROM]], [[Random Access Memory|RAM]] was only used for storing data, and this complicated the life5 KB (796 words) - 16:01, 14 July 2023
- '''Random Access Memory''' (often given as '''RAM''') is slang term for a computer's [[main ...disk]] [[secondary storage]] (although technically disks are also [[random access]] - unlike, say, [[magnetic tape]] secondary storage).457 bytes (64 words) - 13:25, 20 November 2023
- '''Dynamic RAM''' ('dynamic random-access memory'), usually abbreviated as '''DRAM''', is currently the ubiquitous [[ ...he idea which led to IBM's 1968 patent on single-transistor dynamic random access memory2 KB (240 words) - 02:30, 17 February 2024
- ...rd), protected by [[parity]]; cache control logic inspects [[Direct Memory Access|DMA]] transfers on the QBUS and invalidates cache entries for [[main memory2 KB (355 words) - 21:05, 2 July 2023
- ...terrupts, or either can be used to provide the device with [[Direct Memory Access|DMA]] capability.5 KB (820 words) - 04:04, 28 November 2023
- library suitable for one-pass access by _l_d(1).1 KB (152 words) - 16:40, 26 October 2009
- -u Use time of last access instead of last modification4 KB (571 words) - 16:42, 26 October 2009
- must be mounted read-only or errors will occur when access1 KB (224 words) - 16:57, 26 October 2009
- access permissions to files are performed with respect to861 bytes (133 words) - 17:03, 26 October 2009
- A access time must be corrected6 KB (789 words) - 17:21, 26 October 2009
- ...lared `token names'. This allows source files other than '''y.tab.c''' to access the token codes.2 KB (309 words) - 21:34, 26 October 2009
- ...Subsystem]], along with a [[TS04 Tape Transport]]. It used [[Direct Memory Access|DMA]] to transfer both data, and 'command packets', which are commands to t3 KB (369 words) - 20:54, 31 December 2023
- ...ntroller|SPC]] slot. Data is transferred to the host using [[Direct Memory Access|DMA]]; installation of a TUK50 thus requires removal of the [[Non-Processor2 KB (363 words) - 15:09, 24 April 2024
- ...ich automagically corrects single-[[bit]] errors (at a slight penalty in [[access time|response time]] when an error occurs), and detects double-bit errors.8 KB (1,374 words) - 00:43, 30 July 2023
- ...]], the '''M7546'''; data is transferred to the host using [[Direct Memory Access|DMA]].1 KB (160 words) - 23:13, 13 November 2022
- ...erface|RS-232]] [[asynchronous serial line]]s. Output used [[Direct Memory Access|DMA]] (with each line having its own [[buffer]] [[pointer]] and count); inp2 KB (238 words) - 12:05, 17 February 2023
- ...uploaded a copy onto this wiki in uuencoded format. To decode it, simply access the [[boot42|article]], and copy the contents of the quoted text (the begin14 KB (2,267 words) - 16:59, 5 April 2010
- ...uploaded a copy onto this wiki in uuencoded format. To decode it, simply access the [[BootHP|article]], and copy the contents of the quoted text (the begin15 KB (2,380 words) - 18:46, 28 October 2020
- ...ssor, a variant of the [[MC6800|6800]] with 128 bytes of internal [[Random Access Memory|RAM]] and an internal [[clock]] oscillator. There were also five [[63 KB (355 words) - 14:55, 22 April 2024
- ...ns, and watchpoints) instead of writing your own. And the UI provides GUI access to that memory, plus the ability to load/store/modify/examine the memory co4 KB (620 words) - 21:10, 14 January 2024
- ...3,741,824), and a 24bit memory bus (2^24 is 16,777,216), allowing users to access 16MB of RAM. ...build your applications, link with the DOS Extender and now you could have access to 16MB of RAM!5 KB (920 words) - 15:27, 1 January 2019
- ...disks|drives]] were cheap to manufacture; unlike tapes, they are [[random access]]. The media isn't rigid, unlike the [[platter]]s in [[Disk#Recent developm5 KB (682 words) - 21:16, 17 July 2022
- hackers interested in operating systems and 386's with access to minix.4 KB (647 words) - 01:24, 20 December 2018
- devices meant to be used for teletype access should (to should be taken to change the access modes (chmod(1)) on27 KB (4,414 words) - 02:56, 17 January 2023
- teletype access should be named /dev/ttyX, where X is any should be taken to change the access modes (chmod-I) on29 KB (3,738 words) - 02:56, 17 January 2023
- granite is a verb! how to use it? should give access to thief's hideout from to remove it and provide access to the Volcano. Be sure23 KB (3,755 words) - 03:51, 17 December 2018
- <!-- | average access time = xx msec --> It had two heads per surface; not rotationally opposed (to halve maximum access time), but two on each arm; there thus 2,516 usable tracks on each data sur4 KB (542 words) - 03:16, 31 August 2023
- We recommend creating a non-root account and using su(1) for root access.8 KB (1,125 words) - 02:02, 18 November 2010
- one of the files is corrupt and have access to a34 KB (5,687 words) - 18:11, 16 December 2018
- io port access from user processes doesn't randomly work/fail. now must open /dev/mem to get access. (cgd)29 KB (4,794 words) - 18:15, 16 December 2018
- project and access to its works are open to everyone. The project is12 KB (1,841 words) - 06:06, 16 December 2018
- project and access to its works are open to everyone. The project is12 KB (1,699 words) - 06:06, 16 December 2018
- .../M]]! The [http://www.tramm.li/i8080/ project homepage is here], while to access it, just click [http://www.tramm.li/i8080/emu8080.html here].5 KB (150 words) - 14:40, 24 April 2024
- their inability to obtain access to 386BSD, whether licensed with, interested parties could have access to SUPPORTED ver-25 KB (3,920 words) - 05:43, 15 July 2019
- If you do not have access to the internet and electronic mail is your10 KB (1,541 words) - 15:59, 16 December 2018
- Someone gave me access to a SYSVr2 machine!..2 KB (225 words) - 04:17, 17 December 2018
- Seagate's 800 number allows toll-free access to automated self-help CompuServe. To access our technical support forum, type go seagate.25 KB (3,017 words) - 18:47, 13 January 2024
- With MS-DOS installed and able to access a CD-ROM, you will need a blank floppy image, in addition to either an ISO If you have access to Visual C++ 1.0 32bit you'll be in luck as you can rebuild a few things.6 KB (997 words) - 11:22, 9 June 2023
- ...of shipping [[database]] [[application]]s prior to the rise of [[Microsoft Access]]. Clipper applications ran under [[MS-DOS]]. As time went by there were e566 bytes (85 words) - 18:37, 18 December 2018
- RP07: 516 MB HD, 1300 KB/s, 31.3 average access, 23 ms average seek, 5 ms track-to-track seek time, 3633 rpm787 bytes (114 words) - 03:21, 11 November 2023
- | average access time = 42.5 msec (RM02)<br>38.3 msec (RM03)4 KB (533 words) - 17:08, 15 August 2023
- ...6 MB [[MASSBUS]] [[removable-pack disk]] drive, 1200 KB/s, 31.3 ms average access time, 23 ms average seek time, 6 ms track-to-track seek, 3600 RPM. It was [1 KB (177 words) - 18:09, 15 August 2023
- | average access time = 38.3 msec ...rives were supported per controller; drives could be dual-ported, to allow access from two different controllers.2 KB (297 words) - 00:39, 15 August 2023
- | average access time = 50.3 msec4 KB (524 words) - 10:36, 31 August 2023
- | average access time = 27 msec2 KB (280 words) - 10:35, 31 August 2023
- | average access time = 33 msec It had two heads per surface; not rotationally opposed (to halve maximum access time), but two on each arm; there thus 1,092 usable tracks on each surface.2 KB (332 words) - 03:16, 31 August 2023
- | average access time = 33.3 msec It had two heads per surface; not rotationally opposed (to halve maximum access time), but two on each arm; there were thus 1,122 usable tracks on each dat3 KB (355 words) - 16:23, 18 August 2023
- | average access time = 32.3 msec It had two heads per surface; not rotationally opposed (to halve maximum access time), but two on each arm; there thus 2,846 usable tracks on each data sur2 KB (306 words) - 03:12, 31 August 2023
- random access storage devices utilizing nonremovable 5 -inch disks as storage media. Each disk surface employs one movable head to access19 KB (2,330 words) - 14:58, 5 January 2024
- | average access time = 164 msec2 KB (284 words) - 14:45, 15 September 2023
- Average access time using [[random access]] was 9.3 seconds; maximum was 28. Data was verified by a [[checksum]] on e3 KB (373 words) - 03:13, 23 August 2022
- '''DECtape II''' was a low-cost, low-performance [[random access]] [[magnetic tape]] [[secondary storage]] system, proprietary to [[Digital1 KB (166 words) - 16:04, 30 May 2022
- ...ssor, a variant of the [[MC6800|6800]] with 128 bytes of internal [[Random Access Memory|RAM]] and an internal clock oscillator. There was also a [[6821 PIA|3 KB (409 words) - 20:32, 23 April 2024
- ...pment team didn't have a machine to examine, they used what they could get access to, so the process took rather long time.4 KB (587 words) - 00:38, 2 January 2024
- ...ter which process is running. The other special segment is set up to allow access to the [[UNIBUS]]'s so-called 'I/O Page', which holds [[peripheral]] and [[ ...swappable per-process data of each process, and the 8th is set up to allow access to the UNIBUS 'I/O Page'.7 KB (1,161 words) - 15:20, 8 July 2023
- the system namelist for quicker access. taken to change the access modes (chmod(8)) on these files57 KB (8,582 words) - 03:00, 17 January 2023
- ports concurrent read and write access to files (see mt Is a new command which provides easy access to39 KB (5,307 words) - 05:01, 11 December 2018
- 6.3.2 Restricting Access to Data 3-17 Variable Access in Nested Procedures890 KB (107,817 words) - 03:20, 3 January 2024
- o 16MB Addressable Random Access Memory Support 16MB Addressable Random Access Memory Support50 KB (7,113 words) - 03:35, 17 December 2018
- 2.1.7 Direct Device Access 8.2 Network Access627 KB (92,395 words) - 03:42, 17 December 2018
- ...ms, including the ones that are in the section that requires the wedge for access.5 KB (765 words) - 19:00, 26 December 2016
- ==Enabling outside access== To enable root access for all telnet sessions, you will have to edit the /etc/ttys file and chang44 KB (6,192 words) - 09:30, 29 September 2023
- ...KD11-F version includes 4KW of [[Metal Oxide Semiconductor|MOS]] [[Random Access Memory|RAM]] on-board; the KD11-H version has the RAM deleted.3 KB (411 words) - 22:06, 20 December 2023
- ...ead-only memory|ROM]] [[chip socket]] on the CPU card, and gives the KUV11 access to the micro-instruction [[bus]]. ...able, but has read-write access to it via the QBUS. That bus also provides access to a number of control [[register]]s on the KUV11.2 KB (337 words) - 21:12, 2 July 2023
- * [[MSV11-L MOS Random-Access Memory|MSV11-L]] - (M8059) * [[MSV11-P MOS Random-Access Memory|MSV11-P]] - (M8067)5 KB (835 words) - 02:21, 20 September 2022
- ** -- Access pattern: round 2 works mod 5, round 3 works mod 3 **19 KB (2,156 words) - 04:05, 17 December 2018
- ...uploaded a copy onto this wiki in uuencoded format. To decode it, simply access the [[boot42|article]], and copy the contents of the quoted text (the begin13 KB (2,077 words) - 16:30, 7 August 2017
- 6.1.2 Faster access........................ 27 permits access to the O_NDELAY (non-blocking I/O)113 KB (13,419 words) - 02:06, 17 December 2018
- ...s the components for the two parity bits.) Enabling parity increased the [[access time]] from 400 nsec to 525 nsec.5 KB (841 words) - 07:14, 25 March 2022
- | average access time = 70 msec2 KB (259 words) - 00:29, 15 August 2023
- ...e C-F connectors (needed for signals for [[interrupt]]s or [[Direct Memory Access|DMA]], for devices which did those), with most UNIBUS signals present in bo4 KB (708 words) - 16:06, 30 March 2023
- ...tachment of [[main memory]] units, while the C Bus allowed [[Direct Memory Access|DMA]] accesss to main memory.11 KB (1,737 words) - 13:06, 2 April 2024
- ...ats the address and data buses and the R/W line. External devices can then access memory for DMA, for example6 KB (1,084 words) - 16:55, 16 February 2024
- ...ts of tag fields for each cache entry, so that the CPU and [[Direct Memory Access|DMA]] from the QBUS can interact with the cache simultaneously. Cache contr2 KB (391 words) - 16:40, 6 February 2024
- As a further feature, on most UNIBUS backplanes, the 'NPG' ([[Direct Memory Access|DMA]] grant line) signal is carried across unused slots by wire jumpers on6 KB (1,060 words) - 16:35, 6 February 2024
- ...a KTJ11-B, it provides means for UNIBUS devices to perform [[Direct Memory Access|DMA]] cycles (mapped to the full 22-bit address space via a [[UNIBUS map]]) | CD1 || PUBMEM || CPU access to UNIBUS4 KB (731 words) - 17:11, 6 February 2024
- Individual pages may be marked 'Private', which means that only access from code running in Private pages is allowed; i.e. information in such pag ...p page has to contain 16 entries (8 Kbytes at 512 bytes per page) to allow access to the device registers (if they are to appear in the same place in the add15 KB (2,571 words) - 22:23, 11 October 2022
- ...PDR contains the segment's length, along with the direction of growth, the access control field (read/only, read/write, etc), a 'dirty' bit (maintained by th ...th || Trapped || Written || colspan=2 | Unused || Direction || colspan=3 | Access Control9 KB (1,311 words) - 18:10, 2 July 2023
- ...'UNIBUS map''' to allow [[Direct Memory Access|DMA]] devices on the UNIBUS access to all of main memory.2 KB (310 words) - 04:15, 7 January 2021
- ...ory, to perform the relocation function. The pager sometimes needed direct access to the internals of the CPU, to properly perform the demand loading functio5 KB (876 words) - 20:01, 22 January 2024
- ...ecture#Addressing modes|operand modes]] other than mode 0, direct register access (for which, as previously mentioned, the Source or Destination major state9 KB (1,356 words) - 23:10, 29 February 2024
- ...1-B does not contain any internal registers to which the CPU does not have access, the term 'register' hereinafter refers to any of the registers in the KT11 * ENB SPOR(3) (6-1): Select scratchpad register for UNIBUS access31 KB (4,983 words) - 18:22, 2 July 2023
- | average access time = 262 ms The average access time of 262 ms is computed as follows:8 KB (1,195 words) - 20:09, 15 August 2023
- #Redirect [[Direct Memory Access]]34 bytes (4 words) - 02:37, 7 November 2016
- '''Direct Memory Access''', usually abbreviated as '''DMA''', refers to a now-very-common technique ...e. In the second, the memory has multiple ports, and the device has direct access to the memory via one of the ports.751 bytes (125 words) - 23:08, 20 October 2021
- The control section is used to allow the [[Central Processing Unit|CPU]] access to device registers implemented in the devices. The data section is 18 (opt5 KB (729 words) - 21:36, 2 December 2023
- ...er-run errors when there was considerable competing UNIBUS [[Direct Memory Access|DMA]] traffic.9 KB (1,351 words) - 14:44, 26 March 2023
- LINC tape was random access, so the drive had the ability to move forward and backwards to the desired * Severo M. Ornstein, [https://archive.computerhistory.org/resources/access/text/2019/03/102785079-05-01-acc.pdf ''Computing in the Middle Ages: A View3 KB (519 words) - 02:13, 28 February 2024
- ...access to the PDP-8's [[main memory]] (the LINC acted as a [[Direct Memory Access|DMA]] peripheral to the PDP-8, using the PDP-8 [[data break]] mechanism). A ...code running in the LINC access to PDP-8 resources; the PDP-8 likewise had access to the resources of the LINC (e.g. the display). When the PDP-8 was in cont2 KB (328 words) - 13:46, 11 July 2023
- DECtape was [[random access]], so the [[magnetic tape drive|drive]] had the ability to move forward and5 KB (736 words) - 14:21, 30 May 2022
- ...nd [[drum]]scould have slow [[access time]]s, since they were not [[random access]]). ...solved all these problems. It was reliable, relatively cheap, fast, random access, and compact (by the standards of the day) - everything that one could want8 KB (1,299 words) - 02:33, 4 March 2024
- Main memory is also used to store data for immediate access by the CPU. Computers which keep instructions and data in the same memory a2 KB (250 words) - 17:10, 11 September 2019
- #REDIRECT [[Random Access Memory]]34 bytes (4 words) - 05:21, 12 November 2016
- #Redirect [[Random Access Memory]]34 bytes (4 words) - 05:21, 12 November 2016
- ==CSR Access== ...them. That is to use the [[UNIBUS map]] (usually used for [[Direct Memory Access|DMA]] cycles from [[peripheral|device]]s to main memory); the [[memory mana8 KB (1,276 words) - 03:23, 6 February 2024
- ...was a [[diode]] matrix), some later computers included high-speed [[Random Access Memory|RAM]] for part of the control store, so that the instruction set cou6 KB (853 words) - 14:25, 22 January 2024
- ...e 'super block'. So a particular FFS partition might be optimized for fast access, or for minimum wasted space.11 KB (1,759 words) - 19:20, 12 June 2023
- ...mum of 512KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.04 µseconds, and the [[cycle time]] is 1.92 µseconds (both fo2 KB (256 words) - 04:17, 1 August 2023
- ...ovides up to 16 [[asynchronous serial line]]s. Output used [[Direct Memory Access|DMA]] (with each line having its own [[buffer]] [[pointer]] and count); on10 KB (1,443 words) - 02:27, 19 February 2023
- ...trol of the UNIBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle.1 KB (212 words) - 18:50, 6 July 2022
- ...s of [[parallel interface]]s for the [[UNIBUS]]. Some used [[Direct Memory Access|DMA]], others were [[programmed I/O]]. * [[DR11-W Direct Memory Access Interface|DR11-W]]: hex single-board replacement for the DR11-B1 KB (156 words) - 23:02, 14 December 2021
- ...ction]]s performed by the CPU to move data - as opposed to [[Direct Memory Access|DMA]], in which the [[peripheral|device]] communicates directly with [[main * [[Direct Memory Access]]1 KB (192 words) - 23:12, 20 October 2021
- ...[[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device.5 KB (766 words) - 03:15, 25 November 2022
- ...artial copy of a larger collection of data, implemented in such a way that access to the data copy in the cache is faster than to that in the large, full sto1 KB (251 words) - 00:58, 17 May 2023
- ...ing|interleave]] a pair of MM11-D's to provide reduced effective average [[access time]]s.2 KB (376 words) - 19:54, 30 July 2023
- ...o that the device can either start an [[interrupt]], or do [[Direct Memory Access|DMA]] transfer(s) to [[main memory]].1 KB (194 words) - 18:42, 11 November 2019
- ...ce controller]]s that their request for [[interrupt]]s and [[Direct Memory Access|DMA]] have been [[bus grant|granted]] (hence the name).2 KB (281 words) - 01:01, 14 February 2023
- * Has a general purpose [[file system]] with various types of access and protection modes * Has a Monitor Call System to provide user access to input / output functions, string functions, formatting routines and file1 KB (181 words) - 15:15, 9 September 2022
- * two NCR Dual Disc units with capacity of 8 million 16 bit word, average access time 45 ms * one Vermont drum, capacity 256K 16 bit words, access time 10 ms average2 KB (244 words) - 15:14, 9 September 2022
- ...), the owner of the file, the file's protection, and last modification and access times, etc.7 KB (1,147 words) - 14:34, 14 June 2023
- ...AB. DEC had a number of problems with 'corner cases' (e.g. [[Direct Memory Access|DMA]] during certain floating point instructions), and had to issue revised2 KB (276 words) - 21:06, 2 July 2023
- With the advent of the 10 Mbit/second Ethernet, which had 48-bit [[Media Access Control Address|physical addresses]] (so that all Ethernet [[network interf1 KB (207 words) - 18:14, 12 December 2023
- The 48-bit physical address of the DIX Ethernet is known as the [[Media Access Control Address]] (short form: 'MAC Address' or just: 'MAC'), sometimes 'Et Originally, Ethernet was a [[Carrier-Sense Multiple Access with Collision Detection]] (CSMA-CD) [[bus]] (i.e. a shared [[broadcast]] c8 KB (1,199 words) - 22:00, 5 October 2023
- ...]]s usually include registers too. For the ones which are part of the CPU, access to them is very fast - usually faster than main memory.1 KB (173 words) - 13:10, 14 May 2021
- ...h, information may be in [[main memory|primary storage]] (usually [[Random Access Memory|RAM]]) or in [[secondary storage]] (usually [[disk]]), and the [[ope3 KB (536 words) - 02:10, 16 December 2018
- ...[[multi-processor]], with all the [[Central Processing Unit|CPUs]] sharing access to a collection of [[multi-port memory]] units. All used 36-bit [[word]]s,12 KB (1,837 words) - 19:24, 3 January 2024
- ...sters in each track, and using multiple heads on that track to give faster access to the contents of the registers.2 KB (257 words) - 20:45, 18 March 2024
- ...ke an effort to keep the blocks of a file in close physical proximity, for access speed reasons.)906 bytes (151 words) - 23:06, 16 December 2018
- | average access time = 36.3 msec2 KB (284 words) - 19:38, 23 December 2023
- | average access time = 41.5 msec2 KB (233 words) - 20:45, 10 February 2024
- ...rds.) The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B'). ...UNIBI together. (E.g. in the 'disk' RH11 in the KS10, where the CPU needs access to the device registers, interrupts, etc, which are on UNIBUS 'A', but also6 KB (951 words) - 15:40, 25 February 2022
- ...upports [[interrupt]]s from the UNIBUS adapters, as well as [[diagnostic]] access from the mandatory 'console' subsystem, which is interfaced to the KS10 bus ...e UNIBUS [[address space]] into the KS10's main memory for [[Direct Memory Access|DMA]] operations.8 KB (1,237 words) - 19:48, 14 July 2023
- ...ntage that if a handler is inside a procedure, the handler can easily have access to that procedure's [[automatic variable]]s. (It is hard to do both of thes5 KB (795 words) - 13:10, 10 March 2023
- ...er PDP-11-native peripherals could be supported, including [[Direct Memory Access|DMA]] directly into the PDP-15's memory through the [[MX15-B Memory Multipl4 KB (591 words) - 13:40, 11 July 2023
- | average access time = 62.5 msec2 KB (299 words) - 20:41, 10 February 2024
- ...es from the device), as well as to the [[UNIBUS]] (for [[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]). ...eads and writes go directly to the actual main memory (although the RH70's access to the main memory bus is controlled by the cache). A write to a main memor2 KB (318 words) - 15:45, 25 February 2022
- ...e backplane wiring for [[debug]]ging. The unit could rotate to give easier access to the boards.2 KB (307 words) - 03:11, 11 July 2023
- ...nect to the M8267 card. (This is all necessitated because the FP11-A needs access to signals carried over the maintenance cables.) ...M8267 card is normally placed on a hex [[extender card]] to allow physical access to internal signals, a special W9042 Extender Board exists, to be used in p4 KB (734 words) - 02:17, 13 October 2022
- ...cess]] Channel Multiplexor Adapter provided high-speed devices with direct access to main memory for data transfers.6 KB (801 words) - 22:14, 9 February 2024
- CTSS provided access to users on terminals connected to [[asynchronous serial line]]s, both loca6 KB (1,011 words) - 16:53, 7 March 2024
- ...l [[main memory]] was [[core memory]], so the term 'semiconductor [[Random Access Memory|RAM]]' was used to indicate the use of ICs to actually hold data.2 KB (279 words) - 00:36, 11 January 2024
- ...er [[telephone]] lines were the most common. With the rise of [[Internet]] access over [[cable TV]], cable TV modems became common.547 bytes (86 words) - 20:55, 13 December 2018
- ...PDP-15's [[Central Processing Unit|CPU]], but also to allow PDP-15 systems access to devices which did not have native PDP-15 support, such as the [[RK05 dis ...CPU, and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIBUS]]) access to the PDP-15's [[main memory]].1 KB (180 words) - 14:48, 28 November 2022
- ...15 [[main memory]] attached to the MX15-B, and also allowed the PDP-15 CPU access to both the PDP-11's memory, and that PDP-15 memory - i.e. it turned both m2 KB (314 words) - 00:35, 1 December 2022
- The LAN was a [[Carrier-Sense Multiple Access with Collision Detection|CSMA-CD]] system modeled on the [[Xerox PARC]] 3 m ...to provide [[mapping]]s from 16-[[bit]] Chaos [[address]]es to the [[Media Access Control Address|48-bit addresses]] used by Ethernet.)8 KB (1,211 words) - 16:55, 10 April 2024
- ...hich could be attached [[terminal]]s, which allowed users at the terminals access to the hosts attached to the ARPANET.4 KB (659 words) - 15:40, 17 March 2024
- ...nt, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] [[peripheral controller|devices]], and ran all read-write cycles from The ENABLE, being a UNIBUS device, had access to none of the information about CPU mode, fetch type, etc. Instead, the EN9 KB (1,569 words) - 15:47, 6 February 2024
- ...'''Maxc2''' (originally capitalized '''MAXC''' - an acronym for 'Multiple Access Xerox Computer') were a pair of [[PDP-10]] clones made at [[Xerox PARC]], a4 KB (657 words) - 01:43, 17 February 2024
- ! Access5 KB (664 words) - 17:27, 7 November 2023
- ...the connected UNIBI. As far as is known, the other machine(s) did not have access to the KA10's memory (unlike with the [[DL10 PDP-11 Data Link|DL10]] and [[ ...age contained the mapping registers, below; unusually for a PDP-10 device, access to its [[register]]s was via the PDP-10 memory bus.) Each Rubin interface p3 KB (402 words) - 17:01, 22 March 2024
- ...crocode]]. The [[data path]] is 7 bits wide, as is the 2048-word [[Random Access Memory|RAM]]. The predecessor VT50 is almost identical, except there is on4 KB (577 words) - 12:26, 16 January 2024
- ...l Ethernet]]s. It was a [[full-duplex]] device, which used [[Direct Memory Access|DMA]] to transfer [[packet]]s directly to and from [[main memory]]. ...today's standards) was that the back-off after a [[Carrier-Sense Multiple Access with Collision Detection|collision]] was implemented by [[software]], in4 KB (553 words) - 03:18, 13 January 2024
- ...ion''' (often given as the acronym, '''CSMA-CD''') is a way of controlling access to a [[Local area network|LAN]] using a [[broadcast]] bus (i.e. a shared br1 KB (181 words) - 16:10, 7 June 2022
- ...located]] to any location in [[main memory]] (either for normal read/write access, or read-only).4 KB (603 words) - 14:51, 11 June 2023
- ...ies of [[parallel interface]]s for the [[QBUS]]. Some used [[Direct Memory Access|DMA]], others were [[programmed I/O]]. * [[DRV11-B Direct Memory Access Interface|DRV11-B]]: DMA, quad card, 18-bit DMA addresses888 bytes (136 words) - 13:56, 9 June 2020
- ...always has a high-speed [[channel]] or some other form of [[Direct Memory Access]] to transfer data quickly to the computer to which it is attached.514 bytes (80 words) - 16:42, 3 May 2023
- | 0040 || Tried to access a track greater than 774 KB (516 words) - 14:50, 6 November 2022
- They have an identical programming interface; both use [[Direct Memory Access|DMA]] to transfer information between [[main memory]] and the floppy. | 0040 || Tried to access a track greater than 764 KB (536 words) - 15:06, 6 November 2022
- ...y, their controllers) may use either [[programmed I/O]] or [[Direct Memory Access|DMA]] to get data in and out of the [[Central Processing Unit|CPU]] and/or1 KB (167 words) - 02:06, 16 December 2018
- ...can communicate with the main CPU in a number of ways. It may have direct access to the [[main memory]] used by the main CPU, a technique used in the PPUs o1 KB (236 words) - 21:53, 23 September 2022
- ...t-mapped display]] to which the [[Central Processing Unit|CPU]] had direct access, and deployed a group of them in a network/server environment; having so mu4 KB (516 words) - 02:53, 10 January 2024
- ...de words were 32 bits wide), and eventually also 1KW of writeable [[Random Access Memory|RAM]] microcode memory. (The basic ROM microcode more or less emulat ...s, allowing their [[register]]s to appear in the memory address space, for access by [[programmed I/O]]; the last two 'pages' (nothing to do with [[virtual m6 KB (863 words) - 22:39, 3 October 2023
- ...(typically [[Central Processing Unit|CPUs]], [[channel]]s, [[Direct Memory Access|DMA]] [[device controller]]s, etc). If there are multiple banks in the memory, then as long as access requests are spread out fairly evenly across them, it may be possible to pe1 KB (192 words) - 16:36, 15 December 2018
- | instruction speed = 120 μsec (add, excluding memory access) <!-- 525 μsec max --> ...]], with 1000 [[word]]s organized as 100 lines of 10 words each (to reduce access times over fewer, larger lines). The [[Central Processing Unit|CPU]] operat2 KB (319 words) - 01:12, 12 July 2023
- ...re a tremendous range of designs, from 'tightly-coupled' (where they share access to some [[main memory]], which usually has to be [[multi-port memory]]), on1 KB (204 words) - 03:37, 28 November 2023
- ...s, but not address lines); [[Direct Memory Access|DMA]] devices could gain access to the memory via a [[UNIBUS map]] which connected the two, and mapped UNIB4 KB (668 words) - 15:59, 6 February 2024
- ...to a separate [[UNIBUS]]; [[Direct Memory Access|DMA]] devices could gain access to the memory via a [[UNIBUS map]] which connected the two, and also mapped3 KB (456 words) - 21:08, 2 July 2023
- #Redirect [[Direct Memory Access]]34 bytes (4 words) - 16:43, 14 May 2018
- ...[[Multics]]-like tree structured file system including (potentially) full access control. It also provides unique capabilities for running programs as multi7 KB (1,015 words) - 22:43, 15 March 2024
- The [[access time]] is 550 nsec (1250 nsec maximum on [[memory refresh]] conflict), and2 KB (296 words) - 21:14, 21 September 2022
- The [[access time]] is 385 nsec (typical; 1025 nsec maximum on [[memory refresh]] confli2 KB (346 words) - 21:15, 21 September 2022
- Once [[semiconductor]] [[Random Access Memory|RAM]] prices fell low enough, they were replaced with [[bit-mapped d2 KB (302 words) - 02:25, 21 February 2024
- Originally, before [[semiconductor]] [[Random Access Memory|RAM]] prices fell, bit-mapped dislays provided fewer bits per pixel;3 KB (448 words) - 12:21, 27 February 2024
- ...ss time]] of 500 nsec and a [[cycle time]] of 1.2 μsec; the MM11-F had an access time of 400 nsec and a cycle time of 980 nsec.4 KB (667 words) - 19:53, 30 July 2023
- ...line interface#Electrical|EIA]] signal levels are required, as is [[Random Access Memory|RAM]] to hold the screen contents, though.1 KB (164 words) - 04:42, 27 February 2023
- ...Corporation|DEC]]. It was a [[UNIBUS]] device, which used [[Direct Memory Access|DMA]] to retrieve [[display program]]s from [[main memory]]. It was intende2 KB (233 words) - 12:42, 27 February 2024
- ...ding protocols for printer spooling, copying disk packs, page-level remote access to file servers, name lookup, remote management, etc (although some of thes6 KB (926 words) - 16:27, 11 May 2023
- ...'''cycle time''' of the memory is the time period between the start of one access cycle, and the point in time when the memory is ready to accept another one * [[Access time]]1 KB (230 words) - 02:11, 20 September 2022
- ...etimes '''response time''') is the time period between the start of a read access cycle, and the point in time when the data is returned to the requestor. ...n the request arrives, that can delay the memory's response - and thus the access time for that particular cycle.690 bytes (113 words) - 02:11, 20 September 2022
- ...kernel might be 'paged'. Generally, even the higher layers will still have access to operations which ordinary user code is not allowed to use.1 KB (230 words) - 14:11, 29 January 2022
- ...ot all at the same time. Depending on the OS in use, and the settings of [[access control]] parameters (for OS's which have them),the system might prevent on686 bytes (108 words) - 01:36, 16 December 2018
- #Redirect [[Access time]]25 bytes (3 words) - 13:39, 6 July 2018
- ...utomagically corrects single-[[bit]] errors, <!--(at a slight penalty in [[access time|response time]] when an error occurs)--> and detects double-bit errors The [[access time]] is 490-535 nsec (read, typical/max; 215-230 nsec extra on error), 102 KB (345 words) - 17:10, 18 August 2023
- ...ies which have a [[cycle time]] which is significantly longer than their [[access time]]. (The classic example is [[core memory]], which inherently has a muc ...A+1 goes to the other. It was not unknown for interleaving to decrease the access time for a second word by up to 50%, a very significant savings. This is ca2 KB (349 words) - 23:12, 29 July 2023
- An MMV11-A holds 8K [[byte]]s; it has an [[access time]] of 425 nsec, and a [[cycle time]] of 1.15 μsec.2 KB (372 words) - 19:26, 13 July 2023
- use `u.i'. It is undefined to store into u.d and then to access9 KB (1,418 words) - 14:55, 16 January 2023
- * '''''Data break transfers''''', the PDP-8 term for [[Direct Memory Access|DMA]].2 KB (325 words) - 04:52, 19 September 2021
- ...not part of the [[Central Processing Unit|CPU]], but used [[Direct Memory Access|DMA]] for its [[instruction]]s and data.680 bytes (114 words) - 22:25, 22 November 2019
- ...he [[software]] which is used to handle and organize the data, and mediate access to it, is usually called a database management system, usually given as a '376 bytes (61 words) - 14:07, 24 April 2024
- ...that was left to a set of ten 'Peripheral Processing Units', which shared access to the [[main memory]] (which had a 32-way [[memory interleaving|interleave6 KB (789 words) - 17:26, 22 January 2024
- ...nd ran at 12,500 RPM; with a complete rotation time of 4.8 msec, average [[access time]] was thus 2.4 msec (although [[optimum programming]] would reduce tha ...g/pdf/ibm/650/22-6270-1_RAM.pdf 650 Data-processing System with 355 Random Access Memory - Manual of Operation] - system with disk drive(s)4 KB (620 words) - 21:08, 18 March 2024
- ...age over the other two was that it was [[random access]]; the time to gain access to any particular bit was constant.2 KB (354 words) - 15:57, 14 March 2024
- ...were cheap and simple, they had one large drawback; they were not [[random access]]. If the computer needed a value that had just been sent into the delay li2 KB (290 words) - 20:29, 18 March 2024
- ...cluding a 'next [[address]]' field, which was not needed with the [[random access]] [[core memory]] of the 7070. The incompatability with the 705 was harder ...the same two data channels. Each disk had three sets of heads, to minimize access time.3 KB (478 words) - 14:49, 9 April 2024
- ...go to disparate [[address]]es without significant delays; in '''sequential access''' memories, only successive operations to following locations can be done834 bytes (110 words) - 01:56, 24 December 2018
- #Redirect [[Random access]]27 bytes (3 words) - 15:52, 10 October 2018
- ...h automagically corrects single-[[bit]] errors, (at a 70 nsec penalty in [[access time|response time]] when an error occurs) and detects double-bit errors. T The [[access time]] is normally 490-525 nsec (typical/max; 620-675 nsec extra on [[memor3 KB (473 words) - 20:02, 30 July 2023
- ...automagically correct single-[[bit]] errors, and (at a slight penalty in [[access time|response time]] when an error occurs) detect double-bit errors.694 bytes (101 words) - 15:54, 6 February 2024
- #Redirect [[Random Access Memory]]34 bytes (4 words) - 16:41, 21 October 2018
- ...er architecture, long mode is the mode where a 64-bit operating system can access 64-bit instructions and registers. ... Real mode or virtual 8086 mode progr3 KB (536 words) - 16:57, 19 January 2023
- * [[hardware port]] - a means of gaining access to a computer or a sub-system275 bytes (40 words) - 13:11, 19 December 2023
- A '''port''', in [[hardware]] is a means of gaining access to a computer or a sub-system.473 bytes (79 words) - 04:30, 13 December 2018
- ...ys paired with a [[DF10 Data Channel]] unit which performs [[Direct Memory Access|DMA]] to [[main memory]].1 KB (184 words) - 21:59, 8 March 2023
- | average access time = 62.5 msec1 KB (156 words) - 00:32, 15 August 2023
- ...Unit|CPU]]; they are connected to [[peripheral]]s, and usually have direct access to [[main memory]]. ...inframe]] systems; on smaller machines, mechanisms such as [[Direct Memory Access|DMA]] from [[device controller]]s do a lot of what a channel does.1 KB (205 words) - 17:18, 9 April 2024
- ...n pairs of [[contact]]s (which are connected to other pins, for electrical access). How many pairs, and whether they are open or closed when incoming voltage1 KB (167 words) - 05:08, 14 December 2018
- ...ys paired with a [[DF10 Data Channel]] unit which performs [[Direct Memory Access|DMA]] to [[main memory]].1,023 bytes (148 words) - 13:05, 12 November 2023
- That socket gives the FPF11 access to both the [[data bus]] and the [[microinstruction]] bus on the CPU card.2 KB (383 words) - 02:31, 12 October 2022
- ...ious expansions, originally 'Mathematics and Computation'; later 'Multiple Access Computer', 'Machine Aided Cognition', and 'Man and Computer' were added) wa788 bytes (105 words) - 10:22, 10 January 2024
- | average access time = 16.9msec (60Hz), 20.3msec (50Hz)2 KB (258 words) - 22:12, 14 August 2023
- | average access time = 8.5 msec (60Hz), 10.2 msec (50Hz)3 KB (488 words) - 18:37, 14 August 2023
- ...chip also contains [[condition codes]] logic, and a data port which gives access to the [[QBUS]]' data/[[address]] lines.5 KB (773 words) - 22:42, 20 December 2023
- ...ox]] holding a pair of [[DR11-B parallel interface]]s (the [[Direct Memory Access|DMA]] type of DR11 - one for [[packet]] input, and one for output), and a c3 KB (338 words) - 04:19, 30 August 2022
- ...the [[UNIBUS]], either for an [[interrupt]], or performing [[Direct Memory Access|DMA]].2 KB (386 words) - 01:41, 6 July 2023
- #Redirect [[Carrier-Sense Multiple Access with Collision Detection]]68 bytes (7 words) - 01:49, 6 December 2018
- #Redirect [[Carrier-Sense Multiple Access with Collision Detection]]68 bytes (7 words) - 01:50, 6 December 2018
- #REDIRECT [[Direct Access Storage Device]]42 bytes (5 words) - 17:27, 18 December 2018
- They use [[Direct Memory Access|DMA]] to transfer data to and from [[buffer]]s in [[main memory]]. They hav6 KB (797 words) - 21:11, 17 August 2022
- ...PDP-11 memory management]], and used a [[UNIBUS]] for its [[main memory]] access (although a built-in [[cache]] was standard). ...indicates (pg. 4) that devices that do [[interrupt]]s and [[Direct Memory Access|DMA]] must be connected to the I/O UNIBUS, and not to the memory UNIBUS; bu4 KB (536 words) - 12:34, 11 October 2022
- ...[channel]]s for [[mass storage]], such as [[disk]]s, to do [[Direct Memory Access|DMA]]. [[Memory interleaving|Interleaving]] was generally supported between3 KB (431 words) - 03:27, 31 July 2023
- ...0 could contain two to four 32KW memory modules, for a maximum of 128KW; [[access time]] is 0.8 μseconds, and the [[cycle time]] is a maximum of 1.8 μsecon1 KB (231 words) - 13:54, 2 August 2023
- ...16KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.55 μseconds, and a [[cycle time]] of .93 µseconds. It connect1 KB (165 words) - 13:53, 2 August 2023
- ...16KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.60 μseconds, and a [[cycle time]] of 1.65 µseconds. It connec881 bytes (134 words) - 13:53, 2 August 2023
- ...ovided to protect the memory contents. An ME10 contained 16KW; it had an [[access time]] of .55 µseconds (maximum .61 µseconds) and a [[cycle time]] of 1.01 KB (181 words) - 13:55, 2 August 2023
- ...64KW; [[parity]] was provided to protect the memory contents. It had an [[access time]] of 0.61 μseconds, and a [[cycle time]] of 0.95 µseconds.2 KB (271 words) - 12:37, 5 November 2023
- ...imum of 128KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .67 μseconds maximum, and the [[cycle time]] is 1.0 μseconds; [2 KB (342 words) - 12:33, 5 November 2023
- ...imum of 256KW (only 1, 2 or 4 bank operation is supported, however). The [[access time]] is .74 µseconds, and the [[cycle time]] is 1.18 µseconds; [[parity3 KB (407 words) - 12:40, 5 November 2023
- *256 [[kilobyte|KB]] Video [[Random-access memory|RAM]] (The very first cards could be ordered with 64 KB or 128&11 KB (1,681 words) - 12:41, 27 February 2024
- ...l 5150. The entry-level version of the 5150 came with just 16 KB of random-access memory (RAM), which was sufficient to run Cassette BASIC. However, Cassette ...sident code of Cassette BASIC.[2] It added functions such as diskette file access, storing programs on disk, monophonic sound using the PC's built-in speaker9 KB (1,473 words) - 03:37, 16 January 2024
- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[c2 KB (278 words) - 15:50, 24 October 2022
- <!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[c2 KB (355 words) - 15:49, 24 October 2022
- ...ies — 2000A, 2000B, 2000C, High-Speed 2000C, 2000E, 2000F, and 2000/Access.2 KB (342 words) - 19:30, 20 June 2023
- ...ccess to the main memory of the system, to allow it to use [[Direct Memory Access|DMA]] to move data directly from devices to main memory, without needing CP2 KB (294 words) - 12:59, 12 November 2023
- ...the process of deciding which of several competing entities will be given access to a particular resource. In [[hardware]], there are two basic ways to do t395 bytes (59 words) - 08:30, 19 March 2023
- ...two busses are roughly identical (e.g. in [[interrupt]]s, [[Direct Memory Access|DMA]], etc); only the low-level details differ. (E.g. the UNIBUS carries [[2 KB (251 words) - 18:32, 5 December 2022
- The two SYNC registers overlay the buffer registers; access to them is gained via byte UNIBUS operations to odd addresses.6 KB (849 words) - 04:17, 18 February 2023
- Lore found in the printer bin: "In heaven they have instant access computers, in hell they have Primes."2 KB (256 words) - 13:59, 28 September 2019
- ...in the system, either so they can access memory directly ([[Direct Memory Access|DMA]]) or so they can [[interrupt]] the processor and give it an [[interrup DEC's DC010 Direct Memory Access Logic chip [10] uses a delay line just like this but since delay lines are21 KB (3,685 words) - 04:35, 28 November 2023
- ...asynchronous serial line interface|DH11]], in that it used [[Direct Memory Access|DMA]]. ...ven in ones not directly accessible from the UNIBUS); DMA was used to gain access to it. (Perhaps this was early enough in time that [[gate]]s for [[flip-flo8 KB (1,088 words) - 02:24, 19 February 2023
- ...lly refreshed. DRAM rows are refreshed by simply addressing a row. Any row access refreshes that row, no column needs to be strobed for a refresh. ...the KA650. There is no assertion of CAS since there is no need to actually access a specific location, just to refresh a given row.42 KB (5,491 words) - 12:55, 7 May 2024
- * MXV11-AA - 8Kbytes of [[Random Access Memory|RAM]]2 KB (301 words) - 20:47, 13 July 2023
- The board contains 128Kbytes of [[Random Access Memory|RAM]]; it can hold a pair of 2, 4, 8 or 16KB ROMs.2 KB (322 words) - 13:13, 17 February 2023
- ...[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.3 KB (380 words) - 03:54, 10 June 2020
- * [[MSV11-L MOS Random-Access Memory|MSV11-L]] * [[MSV11-P MOS Random-Access Memory|MSV11-P]]616 bytes (99 words) - 21:28, 2 July 2023
- [[Access time]] is 210-230 nsec for reads, and 90-120 nsec for writes; [[cycle time]6 KB (926 words) - 14:10, 22 September 2022
- #Redirect [[MSV11-L MOS Random-Access Memory]]46 bytes (6 words) - 04:15, 7 May 2020
- #Redirect [[MSV11-P MOS Random-Access Memory]]46 bytes (6 words) - 13:42, 7 May 2020
- '''Three cycle data break''' was a form of [[Direct Memory Access|DMA]] for high-speed [[peripheral]]s (usually [[mass storage]]) to [[main m1 KB (235 words) - 22:06, 15 June 2022
- | minimum access time = 260 usec (60Hz)<br>320 usec (60Hz) | average access time = 15.9 msec (60Hz)<br>20.3 usec (60Hz)1 KB (173 words) - 22:13, 14 August 2023
- ...[[bit]] parallel ports, one input, and one output. It uses [[Direct Memory Access|DMA]] to transfer data; it is a [[QBUS#Variable address size|Q22]] device. To gain access to the BAE, reference the BAR; this sets an internal flag which sends the n4 KB (529 words) - 19:12, 2 December 2021
- ...epending on the cabling option chosen (below). Output used [[Direct Memory Access|DMA]] (with each line having its own [[buffer]] [[pointer]] and count); inp6 KB (894 words) - 11:33, 17 February 2023
- ...up on the LSI-11. (The main significant difference is that in the LSI-11, access to the [[Processor Status Word|PS]] requires use of special [[instruction]] * 'raw devices' (which can do [[Direct Memory Access|DMA]] transfers directly from the device to a buffer in the user process' m8 KB (1,243 words) - 21:16, 21 June 2023
- * 'raw devices' (which can do [[Direct Memory Access|DMA]] transfers directly from the device to a buffer in the user's process)7 KB (1,142 words) - 08:14, 8 November 2022
- ...erface|RS-232]] [[asynchronous serial line]]s. Output used [[Direct Memory Access|DMA]] (with each line having its own [[buffer]] [[pointer]] and count); inp2 KB (383 words) - 11:47, 17 February 2023
- ...interface|RS-232]] [[asynchronous serial line]]s, and used [[Direct Memory Access|DMA]] on the output side.5 KB (710 words) - 02:28, 19 February 2023
- ...d to an [[array]] of command [[word]]s) could be read with [[Direct Memory Access|DMA]]; standard in the PDP-4 and -7, optional in the -1. (Connection to the2 KB (242 words) - 03:27, 4 March 2024
- * addition of the access(), tell(), alarm(), pause() and setpgrp() [[system call]]s (these seem to h7 KB (1,109 words) - 16:49, 27 September 2023
- * DEC DC336 QBUS Interface/[[Direct Memory Access|DMA]] Controller ([[DEC part number]] 21-21427-01)1 KB (157 words) - 23:31, 17 August 2022
- ...mum of 128KW; [[parity]] is provided to protect the memory contents. The [[access time]] is 1.00 µseconds, and the [[cycle time]] is 1.92 µseconds (both fo1 KB (191 words) - 04:17, 1 August 2023
- ...ing|interleave]] a pair of MM11-B's to provide reduced effective average [[access time]]s.3 KB (462 words) - 00:45, 30 July 2023
- ...ing|interleave]] a pair of MM11-C's to provide reduced effective average [[access time]]s.2 KB (414 words) - 00:46, 30 July 2023
- ...S08 drives. It used the [[three cycle data break]] form of [[Direct Memory Access|DMA]] to transfer data directly to [[main memory]]. Data transfers can rang525 bytes (79 words) - 20:26, 6 May 2021
- ...S32 drives. It used the [[three cycle data break]] form of [[Direct Memory Access|DMA]] to transfer data directly to [[main memory]].831 bytes (138 words) - 00:50, 30 April 2021
- | memory speed = 2 μsec ([[access time]])<br>8 μsec (read/write [[cycle time]]) [[Direct Memory Access]] for high-speed devices was provided by the [[three cycle data break]] mec6 KB (775 words) - 20:00, 7 February 2024
- To access the setup menus, hold down the CTRL key and press the HELP key twice in qui3 KB (388 words) - 18:55, 16 May 2021
- ...ng bits, to select the field, during the [[Central Processing Unit|CPU]]'s access to memory: the Instruction Field and associated Instruction Buffer Register ...Register, a 3 bit wide register used during [[data break]] [[Direct Memory Access|DMA]] operations, to select the field those cycles go to.4 KB (614 words) - 21:02, 7 August 2022
- .... Unlike the [[DL10 PDP-11 Data Link|DL10]], it didn't use [[Direct Memory Access|DMA]], just [[programmed I/O]]. The device's priority level for [[interrupt3 KB (442 words) - 14:51, 7 March 2023
- The ''' DQ11''' is the earliest [[Direct Memory Access|DMA]] [[synchronous serial line]] [[peripheral|interface]] for the [[UNIBUS The DQ11 has a set of 16 'shadow' registers, access to which is gained by placing the shadow register number in the appropriate8 KB (1,222 words) - 04:17, 18 February 2023
- ...to the PDP-11 (both to reduce the load on the main CPU, but also to allow access to the wide range of peripherals supported on the PDP-11); or it can also f ...nnected to the EBox of the KL10 via the EBus; privileged DTE20's also have access to the diagnostic section of the KL10's Ebus. To the PDP-11, it appears as2 KB (410 words) - 13:14, 12 November 2023
- ...line]] [[peripheral|interface]] for the [[QBUS]]. It used [[Direct Memory Access|DMA]] to transfer data. It could operate in either [[half-duplex]] or [[ful4 KB (508 words) - 03:39, 16 February 2023
- ...cond. It used a 'microprocessor' to drive the lines, using [[Direct Memory Access|DMA]] to the [[PDP-11]]'s [[main memory]] for both input and output. |Secondary Register Access Register || DVSRAR || 7750106 KB (823 words) - 04:24, 18 February 2023
- ...ing|interleave]] a pair of MM11-Y's to provide reduced effective average [[access time]]s.2 KB (244 words) - 00:47, 30 July 2023
- Multiple access user space was a subset of a more general shared memory mechanism (below); * smcreat(path, access, size)3 KB (489 words) - 01:31, 30 December 2022
- ...use [[bus grant line]]s as part of their [[interrupt]]- or [[Direct Memory Access|DMA]]-handling mechanisms. They go in otherwise-empty slots in the [[backpl554 bytes (82 words) - 22:39, 3 December 2021
- ...icrocode]]d processors, having a 24-bit word width, 18-bit addressing, and access to a shared memory. The microcode implements an [[instruction set]] with a2 KB (319 words) - 17:44, 29 April 2024
- ...hard-wired and via dial-up [[modem]]s, allowing [[user]]s at the terminals access to the [[time-sharing]] hosts attached to the ARPANET), ANTS machines provi .../800280.811033 The ARPA Network Terminal System: A New Approach to Network Access], in ''DATACOMM '73: Proceedings of the third ACM symposium on Data communi2 KB (283 words) - 03:12, 30 June 2022
- ...It allowed [[process]]es to be created and terminated, and allowed them access to inter-process communication and timers; allocation and freeing of [[main ...anford.edu/file/druid:jg594pg0466/jg594pg0466.pdf online] at Stanford, but access to it seems to currently be restricted3 KB (461 words) - 16:23, 14 October 2022
- ...could be attached [[terminal]]s, which allowed [[user]]s at the terminals access to the hosts attached to the ARPANET.2 KB (262 words) - 20:25, 17 December 2023
- The '''LH-DH/11 Local/Distant Host Controller''' is a [[Direct Memory Access|DMA]] [[UNIBUS]] [[1822 interface]] produced by [[Advanced Computer Communi3 KB (427 words) - 17:17, 8 November 2021
- The '''MLH-DH/LSI11 Multiple Channel Controller''' is a [[Direct Memory Access|DMA]] [[QBUS]] [[IMP interface]] produced by [[Advanced Computer Communicat3 KB (443 words) - 16:35, 8 November 2021
- ...to-IMP Protocol]] used by the IMPs, PRUs used an alternative, the 'Channel Access Protocol' (CAP), which also includes some of the control mechanisms of the4 KB (557 words) - 20:49, 29 January 2024
- ...ovided an [[1822 interface]] for the [[UNIBUS]] which used [[Direct Memory Access|DMA]] to transfer data to/from [[main memory]].4 KB (500 words) - 23:27, 12 November 2021
- * DC010 - [[Direct Memory Access]] Logic (19-14038-00)2 KB (254 words) - 00:40, 13 July 2023
- ...ontrol of the QBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle.1 KB (190 words) - 04:01, 21 November 2021
- It carried not only the [[Direct Memory Access|DMA]] grant line [[DMA Request and Grant|DMG]], but also the [[interr551 bytes (94 words) - 12:59, 3 December 2021
- [[Application]] [[layer]] devices which allowed users on one side access to similar, but different, services on the other side were also commonly ca638 bytes (95 words) - 18:30, 30 November 2021
- #Redirect [[DR11-W Direct Memory Access Interface]]51 bytes (7 words) - 17:44, 2 December 2021
- ...[[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device. It was a single [[DEC card form fa .../www.bitsavers.org/pdf/dec/unibus/EK-DR11W-UG-004.pdf DR11-W Direct Memory Access Interface Module User's Guide] (EK-DR11W-UG-004)5 KB (746 words) - 17:48, 2 December 2021
- #REDIRECT [[DR11-W Direct Memory Access Interface]]51 bytes (7 words) - 17:41, 2 December 2021
- ...I' machine. When planning for the 2200 started, [[semiconductor]] [[Random Access Memory|RAM]] did not exist yet. Datapoint was using large [[shift register]5 KB (814 words) - 20:05, 4 June 2023
- ...all'' references to a variable evaluate to the variable's [[address]]; for access to the ''contents'', it was necessary to explicitly use the 'contents of' [ ...the original became '''BLISS-10'''. Because of BLISS's goals of providing access to low-level aspects of the host machine, it required changes for the PDP-13 KB (416 words) - 19:05, 8 December 2021
- ...ystem/370|370]] or compatible machine. On the PDP-11 side, [[Direct Memory Access|DMA]] is used to transfer data.2 KB (305 words) - 16:23, 22 January 2024
- <!-- They have an identical programming interface; both use [[Direct Memory Access|DMA]] to transfer information between [[main memory]] and the device.2 KB (244 words) - 20:58, 23 April 2024
- ...net produced by DEC; the BA11-P's (up to two per M9500) swung out for full access, not on slides as with the other BA11's.1 KB (228 words) - 03:23, 11 July 2023
- ...ectly connected, to allow bus read/write cycles (including [[Direct Memory Access|DMA]] cycles) from a master on one to be answered by a slave on the other;3 KB (513 words) - 00:01, 14 January 2022
- In Block Mode, the DA11-B uses [[Direct Memory Access|DMA]] on the source bus to read words in the block, and then uses DMA on th2 KB (286 words) - 04:26, 30 August 2022
- | [[Direct Memory Access]] [[#ref_12|[12]]][[#ref_14|[14]]] | MicroVAX Direct Memory Access (DMA) [[#ref_12|[12]]][[#ref_14|[14]]]36 KB (3,420 words) - 05:36, 5 November 2022
- Memory [[access time]] on read is increased by 150 nsec if there is no error, and by 200 ns3 KB (434 words) - 00:07, 20 April 2024
- | Access Access bits:2 KB (342 words) - 17:07, 6 April 2022
- It provides byte parity. Memory [[access time]] on read is increased by 125 nsec if parity is enabled.<!-- if there4 KB (621 words) - 22:21, 6 July 2022
- | Access Access bits:1 KB (214 words) - 23:15, 5 April 2022
- ...ear; also, all UNIBUS signals are brought up un header pins for convenient access.1 KB (174 words) - 15:31, 9 April 2022
- | Access5 KB (703 words) - 12:29, 27 April 2022
- ...cord-structured' [[input/output|I/O]] (as opposed to the arbitrary storage access now provided by [[UNIX]] and descendant systems, which allow the user to bu536 bytes (80 words) - 01:27, 19 April 2022
- ...of the COVID pandemic, it has unfortunately suspended operations. Remote access remains open to the public.2 KB (217 words) - 17:55, 14 January 2024
- TSR: Colorado Customer Support. What is your access number, please?15 KB (2,569 words) - 08:21, 20 May 2022
- Logicals are usually used to access system files in their standard places.22 KB (3,202 words) - 23:17, 5 September 2022
- ...ended for use with the [[TU55 DECtape Transport]]. It is a [[Direct Memory Access|DMA]] interface, using [[three cycle data break]]; it generates [[interrupt900 bytes (137 words) - 14:35, 30 May 2022
- ...TC08N''', is for PDP8's with a 'negative I/O bus'. It is a [[Direct Memory Access|DMA]] interface, using [[three cycle data break]]; it generates [[interrupt1 KB (162 words) - 14:36, 30 May 2022
- NOT BE TRANSPARENT. FOR YOU TO ACCESS (E.G., TAKE) AN OBJECT SIZES. YOU MAY PUT ANY OBJECT YOU HAVE ACCESS TO (IT NEED NOT BE8 KB (1,230 words) - 12:20, 24 July 2022
- in queue access.101 KB (10,182 words) - 14:04, 2 July 2022
- ...and the dual porting of disk devices. Thus, a single point of failure for access to a disk device could be avoided when VAXcluster configurations were first13 KB (1,908 words) - 19:25, 27 April 2024
- | average access time = 27 msec2 KB (233 words) - 10:28, 31 August 2023
- ===Remote File Access===15 KB (1,849 words) - 16:06, 20 September 2022
- ACCESS PRIVILEGES: ACCESS PRIVILEGES:28 KB (3,686 words) - 19:40, 16 November 2023
- ...o uses [[Carrier-Sense Multiple Access with Collision Detection|CSMA]] for access control to the shared transmission medium, but different in detail from tha3 KB (442 words) - 14:50, 1 May 2024
- The DMC11 uses [[Direct Memory Access|DMA]] to transfer data. It can operate in either [[half-duplex]] or [[full-2 KB (324 words) - 22:46, 13 May 2023
- * the Ethernet Transceiver '''MAU''' (for: '''Media Access Unit'''), and3 KB (426 words) - 22:08, 17 August 2022
- ...is very inconvenient to mount the unit to a Thickwire segment difficult to access, e.g. located in a ceiling plenum.6 KB (955 words) - 17:02, 11 June 2022
- | average access time = 27 msec2 KB (233 words) - 10:29, 31 August 2023
- | average access time = 27 msec2 KB (233 words) - 10:30, 31 August 2023
- ...led video memory), is 256 kB of [[Metal Oxide Semiconductor|MOS]] [[Random Access Memory|RAM]], residing in the Q22-bus address space.2 KB (217 words) - 21:50, 13 February 2024
- ...ode of the [[Central Processing Unit|CPU]], to which the users do not have access, so that they may be protected from each other), the process must use some863 bytes (135 words) - 14:27, 27 June 2022
- in queue access.118 KB (7,116 words) - 14:05, 2 July 2022
- o M8272 C provides random longword aligned 32 bit access capability in queue access.70 KB (7,782 words) - 14:04, 2 July 2022
- Gateway Access = Enabled73 KB (9,059 words) - 20:56, 22 May 2023
- The RIS server must have access to a suitable load device for tape media, e.g. a [[TK50]] or a 9-track [[ma1 KB (217 words) - 10:28, 8 July 2022
- ...ervers provide software that client systems, which may not have disks, can access across the network. Another feature of DMS is that one client can have access to more than one diskless environment.1 KB (225 words) - 09:33, 8 July 2022
- ** The service password needed to gain access to the target node2 KB (341 words) - 20:02, 3 July 2022
- be given access permission to this directory, or a null list to systems you wish to access. First list the name of the remote host80 KB (9,795 words) - 09:39, 10 July 2022
- #Redirect [[Media Access Control Address]]42 bytes (5 words) - 09:51, 9 July 2022
- '''Media Access Control Addresses''' (usually shortened to the acronymic form, '''MAC Addre1 KB (162 words) - 01:15, 11 July 2022
- #Redirect [[Media Access Control Address]]42 bytes (5 words) - 01:15, 11 July 2022
- #Redirect [[Media Access Control Address]]42 bytes (5 words) - 01:16, 11 July 2022
- | average access time = 33.4 msec763 bytes (95 words) - 21:47, 18 February 2024
- ...e purposes. The software to hardware interface is referred to as the port "access protocol." | +-----------+ | Access | +-----------+ |6 KB (698 words) - 21:26, 18 August 2023
- ...[multi-processor]]. The bus has special capabilities to support the shared access to memory required by such a system.3 KB (491 words) - 01:43, 8 May 2024
- space, you may decompress them for faster access. Use SYS$UPDATE:LIBDECOMP.COM112 KB (13,727 words) - 18:09, 30 January 2024
- ...hardware]] level). The lack of refresh also means that it has a constant [[access time]] - there is never a need to wait for a refresh cycle to complete. ...[[bit-mapped display]]s, etc - anyplace where speed and a guaranteed fixed access time are critical. In the early days of [[personal computer]]s, it was some1 KB (183 words) - 02:06, 20 September 2022
- ...ine]] [[peripheral|interface]] for the [[UNIBUS]]. It uses [[Direct Memory Access|DMA]] to transfer data to and from [[main memory]]. The DMR11 can operate i2 KB (315 words) - 23:54, 13 May 2023
- * Automatic Revectoring for transparent access to replaced blocks.4 KB (512 words) - 15:29, 29 December 2023
- With certain restrictions, the HSC50 allows two or more processors to access files on the same disk.9 KB (1,370 words) - 23:47, 28 December 2023
- ...[display program]] held in [[main memory]]. The VSV11 used [[Direct Memory Access|DMA]] to retrieve the display program from the system's main memory, and co3 KB (390 words) - 12:39, 27 February 2024
- ...of a [[UNIBUS]] to a [[QBUS]]. Normal master/slave cycles, [[Direct Memory Access|DMA]] cycles, and [[interrupt]]s can all pass through the DW11. It was a [[1 KB (232 words) - 02:50, 31 August 2022
- For [[Direct Memory Access|DMA]], [[mass storage]] peripherals connected directly to memories (PDP-103 KB (409 words) - 13:38, 12 November 2023
- | Access,,sphere (C)3 KB (444 words) - 23:45, 26 March 2023
- ...been gathered by examining extant [[device driver]]s) is a [[Direct Memory Access|DMA]] [[UNIBUS]] [[synchronous serial line]] [[peripheral]] produced by [[A4 KB (493 words) - 21:22, 17 October 2022
- The '''ACCB''' flag bit signals the presence of access protection data, which is a series of three-byte blocks. The last block ha3 KB (429 words) - 19:21, 12 June 2023
- ...controller]] for the CR04 [[punched card]] reader. It used [[Direct Memory Access|DMA]] to transfer data.4 KB (563 words) - 01:45, 3 November 2022
- ...ain memory]]. PDP-15 [[Central Processing Unit|CPU]]'s and [[Direct Memory Access|DMA]] [[peripheral]]s can be connected to the input ports. A PDP-15 CPU can The MX15-A allows the input ports access to the main memory on a priority basis; port 1 has the highest priority, an972 bytes (161 words) - 16:49, 1 December 2022
- ...ivities were handled by Input/Output Controller modules, similarly sharing access to the memory modules.2 KB (338 words) - 12:50, 5 January 2023
- | Controlled access || No || Yes || Yes ...es were handled by Input/Output Controller modules, which similarly shared access to the memory modules.4 KB (588 words) - 18:00, 12 January 2024
- ....) The streams connect the application to an X [[server]] which has direct access to the [[display]] being used.1 KB (172 words) - 23:01, 9 June 2023
- ...nitially to be an optional add on, but later it was required. The BBA can access the [[frame buffer]] and has its own 256 by 16 bit scratchpad RAM.9 KB (1,261 words) - 08:50, 27 February 2024
- * [[DRV11-B Direct Memory Access Interface]] ** [[MSV11-L MOS Random-Access Memory|MSV11-L]] is covered on pp. 327-3384 KB (644 words) - 19:27, 16 February 2024
- ...ete blocks. ('raw' devices use the [[device controller]]'s [[Direct Memory Access|DMA]] capability to transfers block contents direct to and from [[buffer]]s10 KB (1,838 words) - 21:43, 12 June 2023
- ...command procedures? Thus, ADDUSER.COM (add a user account with appropriate Access Control List Identifiers and a user disk directory), BACKUSER.COM (backup u21 KB (3,330 words) - 03:40, 16 January 2024
- ...'boot server''' (providing boot services) and '''disk server''' (providing access to Cluster-wide mass storage). It was recommended to use dedicated [[VAXser2 KB (360 words) - 14:32, 13 August 2023
- CONNECTED BY A LONG NARROW ACCESS ROOM TO THE SECONDARY (OR Primary-Secondary Hull Access Boom/Access Boom Engine/Cooling Tubes64 KB (10,642 words) - 19:18, 1 February 2024
- ...[multi-processor]]. The bus has special capabilities to support the shared access to memory required by such a system, including support for [[cache coherenc3 KB (396 words) - 01:44, 8 May 2024
- ...ine]] [[peripheral|interface]] for the [[UNIBUS]]. It uses [[Direct Memory Access|DMA]] to transfer data to and from [[main memory]]. The DMP11 can operate i2 KB (277 words) - 00:21, 14 May 2023
- ...ddition to mapping addresses around, the KS11 also definitely limited user access to so-called [[UNIBUS|I/O page]] addresses.5 KB (754 words) - 17:58, 29 February 2024
- ...]] processor, 128k of [[Random Access Memory|RAM]], and no [[Direct Memory Access|DMA]] (although an expansion card was available the offered this and room t5 KB (781 words) - 09:42, 23 May 2023
- ...xamined versus the type of cycle being requested by the processor. If a no access condition is indicated, a "page fault" is generated by the hardware. Otherw ...|| [This feature to be implemented by software on KL-10 using the regular access bit and the "Software" bit.]23 KB (3,961 words) - 17:58, 5 January 2024
- ...are''' was an early computer services company, founded in 1966, which sold access to [[time-sharing]] systems (initially for engineers at aerospace companies * [http://archive.computerhistory.org/resources/access/text/2017/06/102717167-05-01-acc.pdf Oral History of Ann Hardy] - one of th977 bytes (136 words) - 17:45, 10 January 2024
- command can access the swap area, see `/dev/makefile'.33 KB (4,919 words) - 12:31, 21 June 2023
- 061 | VAX PACKETNET SYSTEM INTERFACE ACCESS 0LW | DECSERVER NETWORK ACCESS SOFTWARE15 KB (1,675 words) - 09:17, 25 June 2023
- ** File Access Control List utilities53 KB (6,333 words) - 13:43, 19 July 2023
- ...h gates input to the MB register, thus setting it to PC. SM starts memory access. ...MA/30<br>TI makes a check for indirect addressing. SM starts a new memory access to retrieve the instruction operand.11 KB (1,387 words) - 09:37, 13 August 2023
- ...a RQDX1 containing ‘Rev 9.0' firmware it would no longer be possible to access it with a controller containing "Rev 8.0" firmware unless the Winchester di7 KB (1,107 words) - 05:04, 5 January 2024
- * the ' Selector Channel bus', which supported [[Direct Memory Access|DMA]]2 KB (228 words) - 14:31, 8 August 2023
- ...a [[Central Processing Unit|CPU]], [[Read-only memory|ROM]], and [[Random Access Memory|RAM]], along with all the support [[logic]] needed to create a funct515 bytes (73 words) - 01:57, 30 July 2023
- '''Sector interleaving''' is a technique for speeding up access to sequential data on rotating magnetic media.3 KB (461 words) - 18:11, 21 January 2024
- | average access time = 29 msec770 bytes (103 words) - 16:10, 18 August 2023
- | average access time = 29 msec526 bytes (67 words) - 10:47, 18 August 2023
- ...platter(s), and a hatch in the cover allowed the heads to reach in to gain access to the platter(s).2 KB (394 words) - 14:17, 15 August 2023
- <!-- | average access time = xx msec -->2 KB (306 words) - 11:10, 31 August 2023
- | average access time = 23.6 msec488 bytes (54 words) - 10:46, 18 August 2023
- | average access time = 20.5 msec557 bytes (66 words) - 10:46, 18 August 2023
- | average access time = 13.1 msec555 bytes (66 words) - 10:46, 18 August 2023
- | average access time = 15.1 msec ...uses a 50-pin DSSI interface and a 5-pin Molex power connector, providing access to 852 MB of storage. There are 7 platters, each with 2 heads, for a total2 KB (311 words) - 13:21, 20 November 2023
- | average access time = 15.6 msec487 bytes (54 words) - 12:01, 18 August 2023
- | average access time = 21.6 msec489 bytes (54 words) - 12:11, 18 August 2023
- | average access time = 21.2 msec489 bytes (54 words) - 12:13, 18 August 2023
- | average access time = 18.1 msec489 bytes (54 words) - 12:21, 18 August 2023
- | average access time = 0.25 msec1 KB (169 words) - 14:27, 2 December 2023
- | average access time = 0.25 msec1 KB (170 words) - 14:32, 2 December 2023
- | average access time = 0.25 msec1 KB (149 words) - 14:36, 2 December 2023
- ...SSI buses to provide device access with no single points-of-failure in the access path. ...meters. It also can be used for device formatting and qualification and to access device information.5 KB (710 words) - 00:04, 13 January 2024
- 44Mb, 70Mb and optional 115Mb fixed disks provide ready-access storage for large files and applications, even elaborate data bases. ...options lets you connect Model 60 in a variety of local area networks and access the power of many larger systems.8 KB (1,167 words) - 19:03, 2 January 2024
- <!-- | minimum access time = --> | average access time = 30.5-45.5 msec2 KB (251 words) - 20:22, 23 April 2024
- ...ach. Each page may individually be mapped to some backing store, and have access read/write bits set. Backing store is normally anonymous core memory or fi10 KB (1,580 words) - 14:00, 1 December 2023
- It used [[Direct Memory Access|DMA]] to transfer rasters from the PDP-11's [[main memory]] to the XGP. A r5 KB (869 words) - 13:30, 27 February 2024
- ...st anything there, even the rarest code and devices, if you happen to have access to the right edition.1 KB (183 words) - 22:31, 1 October 2023
- * FILE — remote file system access; mainly for Lisp machines. * MLDEV — remote file system access; mainly for ITS.2 KB (259 words) - 17:41, 12 December 2023
- from more than one system to simultaneously access files. Any still access all files that do not depend on the down system53 KB (6,770 words) - 13:15, 16 November 2023
- ...system application. The PDP-8's code is held in a normal PDP-8 4K [[Random Access Memory|RAM]], the 'control storage memory', and was loaded into the DX10 by3 KB (492 words) - 20:33, 12 February 2024
- ...s]], SDB) with STI; the higher layer [[protocol]]s are adapted to [[random access]] storage needs. STI configurations are slightly more complex than SDI, as3 KB (392 words) - 04:13, 19 April 2024
- ...founded in 1970 as a subsidiary of Golden United Life Insurance. They sold access to [[time-sharing]] systems, for which they used [[PDP-10]]'s heavily (init1 KB (142 words) - 08:22, 16 January 2024
- Access to the additional teletypes is provided by five more bits2 KB (320 words) - 20:42, 10 January 2024
- that blocked access to the NISA applications (Forums, mail). Diagnosing5 KB (817 words) - 06:56, 20 February 2024
- ...[[microcode]]d, with 32K 80-bit [[word]]s of read/write microcode [[Random Access Memory|RAM]]; it had a 32K-word write-through [[cache]]. [[Main memory]] ([1 KB (194 words) - 18:51, 21 January 2024
- ...d transfer data to the [[main memory]] of the machine with [[Direct Memory Access|DMA]], and [[interrupt]] the [[Central Processing Unit|CPU]].5 KB (704 words) - 17:20, 9 April 2024
- X-terminal services Open disk access (any client) Open tape access (any client)9 KB (961 words) - 11:23, 28 January 2024
- <!-- | average access time = 41.5 msec -->2 KB (229 words) - 18:18, 11 February 2024
- <!-- | average access time = 41.5 msec -->2 KB (263 words) - 18:19, 11 February 2024
- ...] allows several [[DF10 Data Channel]]s or [[DX10 Data Channel]]s to share access to a [[PDP-10 Memory Bus]], and thus, to the [[multi-port memory]] banks to788 bytes (124 words) - 01:09, 13 February 2024
- ...story.si.edu/collections/nmah_713496 Intel 1103 1K Bit pMOS Dynamic Random Access Memory (DRAM)] - the writeup may contain an error; it says "a one-transisto2 KB (235 words) - 16:41, 17 February 2024
- ...nough to hold an extended address, the MTC used [[bank switching]] to gain access to all of main memory.6 KB (932 words) - 22:10, 1 March 2024
- ...8-bit [[word]]s, it also had 5 4-word lines (the reduced size gave lower [[access time]]s), 4 2-word lines, and 7 1-word lines; the shorter ones had the role6 KB (855 words) - 03:53, 25 March 2024
- ...ngth [[operand]]s), and 5 single-word lines (the reduced size gave lower [[access time]]s). The shorter ones had the role of [[register]]s in most computers.5 KB (812 words) - 03:52, 25 March 2024
- ...ed around the track, with multiple read [[head]]s, so as to reduce their [[access time]].4 KB (607 words) - 22:47, 1 April 2024
- ...nes had the role of [[register]]s in most computers, and came with lower [[access time]]s); to achieve that, the read and write [[head]]s were placed closer6 KB (870 words) - 22:44, 1 April 2024
- | DHU11 | 16 Line Async Controller w/ DMA Access | Ref | | | | | |... | DMZ32 | 24 Line Async Controller w/ DMA Access | Ref | | | | | |...198 KB (5,881 words) - 23:03, 28 March 2024
- ...may be replaced by a shorter line, such as a 16-word line, for decreased [[access time]] (at the cost of a reduction in available space); line 0 is usually c7 KB (1,005 words) - 12:24, 2 April 2024
- ...including [[SONET]], [[MPLS]], and [[Ethernet]] (where PPP is used to gain access to capabilities available under PPP, such as authentication).2 KB (295 words) - 17:48, 18 April 2024
